公开(公告)号：US6011383A

公开(公告)日：2000-01-04

申请号：US120211

申请日：1998-07-21

申请人： Alvar A. Dean ,  Kenneth J. Goodnow ,  Patrick E. Perry ,  Wilbur D. Pricer ,  William R. Tonti

发明人： Alvar A. Dean ,  Kenneth J. Goodnow ,  Patrick E. Perry ,  Wilbur D. Pricer ,  William R. Tonti

IPC分类号： G06F1/32 ,  G05F1/110 ,  G06F1/00

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02B60/1285

摘要： A low powering apparatus for automatic reduction of power in active and standby modes is disclosed. The low powering apparatus includes a state detector, a margins of safety device and a positioning device. The state detector detects a first or second state, such as a standby state and an active state, that has predominated in a recent past. The margins of safety device indicates safe low power margins in correlation to the detected first or second state. The positioning device adjusts the power level according to the outputs of the state detector and margins of safety device. Thus, the low powering apparatus minimizes the power level of a system at the first or second state without compromising full performance of the system.

摘要翻译： 公开了一种用于在主动和待机模式下自动降低功率的低功率设备。 低功率装置包括状态检测器，安全装置的边缘和定位装置。 状态检测器检测在最近过去占主导地位的第一或第二状态，例如待机状态和活动状态。 安全装置的边缘表示与检测到的第一或第二状态相关的安全低功率余量。 定位装置根据状态检测器的输出和安全装置的余量调整功率水平。 因此，低功率设备使系统在第一或第二状态下的功率水平最小化，而不会影响系统的全部性能。

公开(公告)号：US6097241A

公开(公告)日：2000-08-01

申请号：US159898

申请日：1998-09-24

申请人： Claude L. Bertin ,  Alvar A. Dean ,  Kenneth J. Goodnow ,  Wilbur D. Pricer ,  William R. Tonti

发明人： Claude L. Bertin ,  Alvar A. Dean ,  Kenneth J. Goodnow ,  Wilbur D. Pricer ,  William R. Tonti

IPC分类号： G06F1/32 ,  H03K3/01

CPC分类号： G06F1/3203 ,  G06F1/3296 ,  Y02B60/1285

摘要： An integrated circuit such as an ASIC device having partitioned functional units with independent threshold voltage control. A first partition is always operated in a normal mode, while subsequent partitions are maintained in a standby mode until a transition is detected at the input of the first partition. The subsequent partitions are switched to the normal mode by lowering the body voltage applied to the devices with each partition. A pulse stretcher is used to keep a partition in a normal mode for a predetermined period of time after the transition is detected.

摘要翻译： 诸如具有独立阈值电压控制的具有分区功能单元的ASIC器件的集成电路。 第一分区总是以正常模式操作，而后续分区保持在待机模式，直到在第一分区的输入处检测到转换。 随后的分区通过降低施加到每个分区的设备的体电压而切换到正常模式。 在检测到转换之后，使用脉冲展开器将分区保持在正常模式下预定的时间段。

公开(公告)号：US06532520B1

公开(公告)日：2003-03-11

申请号：US09394965

申请日：1999-09-10

申请人： Alvar A. Dean ,  Marc R. Faucher ,  John W. Goetz ,  Kenneth J. Goodnow ,  Paul T. Gutwin ,  Stephen W. Mahin ,  Wilbur D. Pricer

发明人： Alvar A. Dean ,  Marc R. Faucher ,  John W. Goetz ,  Kenneth J. Goodnow ,  Paul T. Gutwin ,  Stephen W. Mahin ,  Wilbur D. Pricer

IPC分类号： G06F1200

CPC分类号： G06F12/121 ,  G06F12/127 ,  G06F2212/1021 ,  G06F2212/6042

摘要： A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.

摘要翻译： 提供了一种方法和装置，用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。 高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数，并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。 然后，响应于检测到的预选阈值的交叉，调整统一高速缓存的替换算法，该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。 替换算法优选地是LRU算法，其中调整步骤包括递增第一类型数据线的年龄指示。 用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器，其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数，并且当计数器的计数超过时，在第一计数器输出上输出第一逻辑状态 第一预定计数。 耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态，增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。

公开(公告)号：US08513948B2

公开(公告)日：2013-08-20

申请号：US12951515

申请日：2010-11-22

申请人： Jonathan P. Ebbers ,  Kenneth J. Goodnow ,  Stephen Gerard Shuma ,  Peter A. Twombly

发明人： Jonathan P. Ebbers ,  Kenneth J. Goodnow ,  Stephen Gerard Shuma ,  Peter A. Twombly

IPC分类号： G01R31/327 ,  G01R27/26

CPC分类号： B81C99/003 ,  B81B2203/0118

摘要： A MEMS component is monitored to determine its status. Sensors are deployed to sense the MEMS component and produce detection signals that are analyzed to determine the MEMS component state. An indicator device alerts a user of the status, particularly if the MEMS component has failed. Additionally, the MEMS component monitoring system may be practiced as a design structure encoded on computer readable storage media as part of a circuit design system.

摘要翻译： 监测MEMS组件以确定其状态。 部署传感器以感测MEMS组件并产生被分析以检测MEMS组件状态的检测信号。 指示器设备向用户通知状态，特别是如果MEMS组件出现故障。 另外，作为电路设计系统的一部分，可以将MEMS部件监视系统实施为在计算机可读存储介质上编码的设计结构。

公开(公告)号：US08020137B2

公开(公告)日：2011-09-13

申请号：US11957626

申请日：2007-12-17

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth requirement of the integrated circuit. The input/output element includes one or more switching devices that connect the input/output pin to an external element, such as a power supply or external signal path. The input/output element also includes one or more switching devices that connect the input/output pin to an internal element, such as a power network or internal signal line.

摘要翻译： 用于选择性地将集成电路连接到集成电路外部的元件的电路的设计结构。 该电路包括输入/​​输出元件，其根据功率需求或集成电路的信号带宽需求选择性地连接输入/输出引脚。 输入/输出元件包括将输入/输出引脚连接到诸如电源或外部信号路径的外部元件的一个或多个开关器件。 输入/输出元件还包括将输入/输出引脚连接到诸如电力网络或内部信号线的内部元件的一个或多个开关器件。

公开(公告)号：US20110099527A1

公开(公告)日：2011-04-28

申请号：US12605417

申请日：2009-10-26

申请人： Adam J. Courchesne ,  Johnathan P. Ebbers ,  Kenneth J. Goodnow ,  Suzanne Granato ,  Eze Kamanu ,  Kyle E. Schneider ,  Peter A. Twombly

发明人： Adam J. Courchesne ,  Johnathan P. Ebbers ,  Kenneth J. Goodnow ,  Suzanne Granato ,  Eze Kamanu ,  Kyle E. Schneider ,  Peter A. Twombly

IPC分类号： G06F17/50

CPC分类号： G06F15/7867

摘要： A method configures a plurality of circuit elements for execution of an application in a first configuration. The method monitors the execution of the application on the plurality of circuit elements to produce monitoring information, using a computerized device, and stores the monitoring information in a storage structure. The method selectively communicates the monitoring information to an external element separate from the computerized device. The external element transforms the first configuration into a second configuration based on the monitoring information. The computerized device receives the second configuration from the external element and reconfigures the plurality of elements into the second configuration.

摘要翻译： 一种方法在第一配置中配置用于执行应用的多个电路元件。 该方法监视多个电路元件上的应用的执行，使用计算机化的设备产生监视信息，并将监视信息存储在存储结构中。 该方法选择性地将监视信息传送到与计算机化设备分开的外部元件。 外部元素基于监视信息将第一配置转换成第二配置。 计算机化设备从外部元件接收第二配置，并将多个元件重新配置成第二配置。

公开(公告)号：US20090273239A1

公开(公告)日：2009-11-05

申请号：US12113999

申请日：2008-05-02

申请人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

发明人： Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly

IPC分类号： H02J1/00

CPC分类号： G06F1/26 ,  Y10T307/438

摘要： A system for dynamic integrated circuit power distribution and control is disclosed. The system includes an external power consumption target generator configured to generate a power dissipation target for one or more integrated circuits. The system also includes a first integrated circuit that includes an IC power control unit coupled to the external power consumption target generator. The first integrated circuit also includes a first plurality of functional units, each functional unit of the first plurality including a unit power level control and a first power control grid coupling the IC power control unit to one or more of the first plurality of functional units. The IC power control unit is configured to generate a mode control signal which places at least one of plurality of functional units into a first mode of operation based upon the power consumption target.

摘要翻译： 公开了一种动态集成电路配电控制系统。 该系统包括被配置为产生一个或多个集成电路的功耗目标的外部功耗目标发生器。 该系统还包括第一集成电路，其包括耦合到外部功耗目标发生器的IC功率控制单元。 第一集成电路还包括第一多个功能单元，第一多个功能单元的每个功能单元包括单元功率电平控制和将IC功率控制单元耦合到第一多个功能单元中的一个或多个的第一功率控制网格。 IC功率控制单元被配置为基于功耗目标产生将多个功能单元中的至少一个功能单元置于第一操作模式的模式控制信号。

公开(公告)号：US07545165B2

公开(公告)日：2009-06-09

申请号：US11621175

申请日：2007-01-09

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC systems architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-clip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributers; the noise event arbiter determining when each noise contributer may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributer as to when permission is granted to execute its operations.

摘要翻译： 集成电路（IC）系统架构允许通过提供避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件的手段来减少片上或跨芯片的瞬态噪声预算。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。 调度片上噪声事件以避免同时的主动瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者同时接收多个请求操作; 噪声事件仲裁器确定每个噪声分配器何时可以基于预先建立的dI / dt预算来执行操作; 并且噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

公开(公告)号：US20090119625A1

公开(公告)日：2009-05-07

申请号：US11934804

申请日：2007-11-05

申请人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

发明人： Corey K. Barrows ,  Kenneth J. Goodnow ,  Stephen G. Shuma ,  Peter A. Twombly ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.

摘要翻译： 一种设计结构集成电路（IC）系统架构，其允许通过提供一种方法来减少片上或跨芯片的瞬态噪声预算，以避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件， 被披露。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。 调度片上噪声事件以避免同时有效的瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者接收多个请求操作的请求; 噪声事件仲裁者确定每个噪声贡献者何时可以基于预先建立的dI / dt预算执行操作; 噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

公开(公告)号：US20090094566A1

公开(公告)日：2009-04-09

申请号：US12105883

申请日：2008-04-18

申请人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

发明人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

IPC分类号： G06F17/50

CPC分类号： G06K19/067

摘要： Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.

摘要翻译： 公开了用于片上识别电路的设计结构。 在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。 每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。 在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。 第一和第二导体在芯片之间交替。 由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。 在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。