公开(公告)号：US11094277B2

公开(公告)日：2021-08-17

申请号：US16149432

申请日：2018-10-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Guangliang Shang ,  Xing Yao ,  Lijun Yuan ,  Zhichong Wang ,  Mingfu Han ,  Yinglong Huang

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus.

公开(公告)号：US10943552B2

公开(公告)日：2021-03-09

申请号：US15768309

申请日：2017-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seungwoo Han ,  Guangliang Shang ,  Haoliang Zheng ,  Xing Yao ,  Zhichong Wang ,  Mingfu Han ,  Lijun Yuan ,  Yunsik Im ,  Jing Lv ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266

Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

公开(公告)号：US10699627B2

公开(公告)日：2020-06-30

申请号：US16287403

申请日：2019-02-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yoonsung Um ,  Mingfu Han ,  Lijun Yuan ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng

IPC: G09G3/20

Abstract: A driving method of a display panel, a display panel and a display device are disclosed. The method includes: for a first row of sub-pixels and a second row, adjacent to the first row, of sub-pixels, during a display period of a first frame image, inputting data signals to the first row of sub-pixels in a first order, and inputting data signals to the second row of sub-pixels in a second order opposite to the first order; and during a display period of a second frame image adjacent to the first frame image, inputting data signals to the first row of sub-pixels in the second order and inputting data signals to the second row of sub-pixels in the first order.

公开(公告)号：US20200090611A1

公开(公告)日：2020-03-19

申请号：US15751066

申请日：2017-07-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Guangliang Shang ,  Xing Yao ,  Seung Woo Han ,  Jiha Kim ,  Haoliang Zheng ,  Lijun Yuan ,  Zhichong Wang

IPC: G09G3/36

Abstract: The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.

公开(公告)号：US10559282B2

公开(公告)日：2020-02-11

申请号：US15793957

申请日：2017-10-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Jung Chul Gyu ,  Seung Woo Han ,  Haoliang Zheng ,  Mingfu Han ,  Zhihe Jin ,  Im- Yun- Sik ,  Jing Lv ,  Xue Dong

IPC: G09G5/22 ,  G09G3/20 ,  G09G5/00 ,  G09G3/36

Abstract: The present disclosure relates to a pixel driving circuit for switching display resolution, a driving method thereof, and a display apparatus. The pixel driving circuit comprises: r first data lines and k second data lines, each of the first data lines has a first switch provided thereon, and is connected to at least one of the k second data lines through at least one second switch respectively, and the first switch and the second switch are connected to a signal control unit which is configured to control the first switch to be turned on and the second switch to be turned off when display is to be performed at a first resolution, and control the first switch to be turned off and the second switch to be turned on when display is to be performed at a second resolution.

公开(公告)号：US10540938B2

公开(公告)日：2020-01-21

申请号：US15768948

申请日：2017-10-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seung Woo Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng ,  Mingfu Han ,  Zhichong Wang ,  Lijun Yuan ,  Yun Sik Im ,  Jing Lv ,  Yinglong Huang ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266 ,  G09G3/20 ,  G11C19/18

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

公开(公告)号：US10453413B2

公开(公告)日：2019-10-22

申请号：US15565756

申请日：2017-03-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Guangliang Shang

IPC: G09G3/36 ,  G09G3/20 ,  G09G3/3225 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1368

Abstract: The present application discloses an array substrate comprising a plurality of gate lines and a plurality of data lines crossing over each other thereby defining an array of a plurality of sub-pixel areas, each sub-pixel area comprising a pixel electrode and multiple switching transistors having respective gate electrodes coupled to multiple different gate lines, wherein the pixel electrode is configured to be charged by a data signal from a data line only with all the multiple switching transistors being turned on concurrently during a pixel electrode charging period by an effective voltage level applied on the respective multiple different gate lines.

公开(公告)号：US20190279583A1

公开(公告)日：2019-09-12

申请号：US16340508

申请日：2018-08-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Yaoqiu Jing ,  Yifang Chu ,  Xue Dong

IPC: G09G3/36

Abstract: A method and a device for detecting pixel charging compensation, and a method and a device for compensating pixel charging are provided. The method for detecting includes: dividing a display area of a display panel into at least two compensation regions; detecting a first brightness of a target pixel in each compensation region; and calculating a compensation time duration for charging the target pixel according to a difference between the first brightness and the set brightness; and setting the compensation time duration to be a compensation time duration for charging the pixels in the compensation region in which the target pixel is located.

公开(公告)号：US10330975B2

公开(公告)日：2019-06-25

申请号：US15794298

申请日：2017-10-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhihe Jin ,  Seungwoo Han ,  Mingfu Han ,  Xing Yao ,  Guangliang Shang ,  Zhichong Wang ,  Lijun Yuan ,  Haoliang Zheng ,  Yunsik Im

IPC: G02F1/133 ,  G02F1/13357 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/19

Abstract: The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units.

公开(公告)号：US20180336842A1

公开(公告)日：2018-11-22

申请号：US15533761

申请日：2016-12-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Guangliang Shang

IPC: G09G3/34 ,  H04N5/369

CPC classification number: G09G3/34 ,  G09G3/3685 ,  G09G2320/0252 ,  H04N5/3698

Abstract: The present application discloses a method for driving a display panel, including receiving one or more frames of image data one after another each of which having image data for a plurality of subpixels in the display panel; determining an initial driving voltage corresponding to one subpixel of the plurality of subpixels based on each frame of image data; determining an overdrive voltage corresponding to the one subpixel based on the initial driving voltage and a compensation voltage corresponding to the one subpixel, wherein an amplitude of the overdrive voltage is greater than an amplitude of the initial driving voltage; and applying the overdrive voltage to the one subpixel for an overdrive time period followed by applying the initial driving voltage to a same one subpixel for displaying a subpixel image associated with each frame of image data.