公开(公告)号：US07112481B2

公开(公告)日：2006-09-26

申请号：US11254929

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

摘要翻译： 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

公开(公告)号：US07102234B2

公开(公告)日：2006-09-05

申请号：US10827064

申请日：2004-04-19

申请人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

发明人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L21/28518

摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.

摘要翻译： 一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自 由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层 金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。 当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相 的Ni硅化物。

公开(公告)号：US07067368B1

公开(公告)日：2006-06-27

申请号：US11254934

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US07064025B1

公开(公告)日：2006-06-20

申请号：US10904884

申请日：2004-12-02

申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US20060121664A1

公开(公告)日：2006-06-08

申请号：US11254929

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

发明人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US06989322B2

公开(公告)日：2006-01-24

申请号：US10707175

申请日：2003-11-25

申请人： Oleg G. Gluschenkov ,  Cyril Cabral, Jr. ,  Omer Dokumaci ,  Christian Lavoie

发明人： Oleg G. Gluschenkov ,  Cyril Cabral, Jr. ,  Omer Dokumaci ,  Christian Lavoie

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/0847 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide and the channel.

摘要翻译： 通过使用薄硅化停止扩展来形成MOSFET器件中的非常低的电阻，其既用作硅化“阻挡”势垒，又作为源/漏硅化物区域和MOSFET的沟道区之间的薄界面层。 通过作为硅化停止，硅化 - 停止扩展限制硅化，并且不被源/漏硅化物破坏。 这允许在硅化物和沟道之间形成非常薄的，高掺杂的硅化 - 停止延伸，在硅化物和沟道之间提供基本理想的低串联电阻接口。

公开(公告)号：US06987050B2

公开(公告)日：2006-01-17

申请号：US09902483

申请日：2001-07-11

申请人： Cyril Cabral, Jr. ,  Kevin Kok Chan ,  Guy Moshe Cohen ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Paul Michael Solomon

发明人： Cyril Cabral, Jr. ,  Kevin Kok Chan ,  Guy Moshe Cohen ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Paul Michael Solomon

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/66772 ,  H01L21/28518 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/78

摘要： A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

摘要翻译： 一种用于制造半导体器件用硅化物的方法（及其结构）包括在硅衬底上沉积金属或其合金，使金属或合金反应形成第一硅化物相，蚀刻任何未反应的金属，沉积硅 在第一硅化物相上，使硅帽层反应形成第二硅化物相，并且蚀刻任何未反应的硅。 衬底可以是绝缘体上硅（SOI）衬底或体硅衬底。

公开(公告)号：US06905560B2

公开(公告)日：2005-06-14

申请号：US10334464

申请日：2002-12-31

申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  James M. E. Harper ,  Christian Lavoie

发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  James M. E. Harper ,  Christian Lavoie

IPC分类号： C04B35/58 ,  C22F1/00 ,  C23C10/00 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/60 ,  H01L21/768

CPC分类号： C04B35/58 ,  C04B35/58085 ,  C04B2235/40 ,  C04B2235/404 ,  C04B2235/405 ,  C04B2235/408 ,  C23C26/00 ,  C23C30/00 ,  H01L21/28518 ,  H01L21/76889

摘要： A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.

公开(公告)号：US06809030B2

公开(公告)日：2004-10-26

申请号：US10185547

申请日：2002-06-28

申请人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Kirk David Peterson ,  Robert Joseph Purtell ,  Ronnen Andrew Roy ,  Jean Louise Jordan-Sweet ,  Yun Yu Wang

发明人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Kirk David Peterson ,  Robert Joseph Purtell ,  Ronnen Andrew Roy ,  Jean Louise Jordan-Sweet ,  Yun Yu Wang

IPC分类号： H01L2144

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

摘要翻译： 本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。 本发明的方法包括（a）形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是含硅基体上的合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

公开(公告)号：US06753606B2

公开(公告)日：2004-06-22

申请号：US09994954

申请日：2001-11-27

申请人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

发明人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

IPC分类号： H01L2348

CPC分类号： H01L21/28518

摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.

摘要翻译： 一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自 由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层 金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。 当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相 的Ni硅化物。