公开(公告)号：US08445974B2

公开(公告)日：2013-05-21

申请号：US12683602

申请日：2010-01-07

申请人： Dureseti Chidambarrao ,  Sunfei Fang ,  Yue Liang ,  Xiaojun Yu ,  Jun Yuan

发明人： Dureseti Chidambarrao ,  Sunfei Fang ,  Yue Liang ,  Xiaojun Yu ,  Jun Yuan

IPC分类号： H01L21/02

CPC分类号： H01L27/092 ,  H01L21/823857 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78

摘要： A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.

摘要翻译： 提供一种半导体结构，其包括位于半导体结构的表面上的至少一个非对称栅极堆叠。 所述至少一个非对称栅极堆叠包括从底部到顶部的高k栅极电介质，倾斜阈值电压调节材料层和栅极导体。 还提供了一种形成这种半导体结构的方法，其中在形成相对于半导体结构的水平表面倾斜的沉积倾斜的阈值电压调节材料层中使用视线沉积工艺。

公开(公告)号：US07923365B2

公开(公告)日：2011-04-12

申请号：US11874118

申请日：2007-10-17

申请人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

发明人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

摘要翻译： 形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。 当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。 然后从栅电极的侧壁去除牺牲隔离物。 然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管） 。

公开(公告)号：US07863693B2

公开(公告)日：2011-01-04

申请号：US12013622

申请日：2008-01-14

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan

IPC分类号： H01L21/02

CPC分类号： H01L21/823871 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

摘要翻译： 本发明的实施例提供一种形成与半导体器件接触的导电柱的方法。 该方法包括形成覆盖半导体器件的保护层; 选择性地将开口向下蚀刻通过保护层到达半导体器件的接触区域，该开口远离半导体器件的保护区域; 并用导电材料填充开口以形成导电柱。 一个实施例还可以包括直接在半导体器件的顶部上形成电介质衬垫，以及在电介质衬垫的顶部上形成保护层。 本发明的实施例还提供由其制成的半导体器件。

公开(公告)号：US20100029072A1

公开(公告)日：2010-02-04

申请号：US12507887

申请日：2009-07-23

申请人： Jae-Eon Park ,  Jun-Keun Kwak ,  Jin-Woo Choi ,  Sunfei Fang ,  Jiang Yan

发明人： Jae-Eon Park ,  Jun-Keun Kwak ,  Jin-Woo Choi ,  Sunfei Fang ,  Jiang Yan

IPC分类号： H01L21/768 ,  H01L21/8234

CPC分类号： H01L21/823475 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/823425

摘要： Methods of forming integrated circuit devices include forming an electrically insulating layer having a contact hole therein, on a substrate, and then depositing an electrically insulating liner onto a sidewall of the contact hole using an atomic layer deposition (ALD) technique. This electrically insulating liner, which may include gelatinous silica or silicon dioxide, for example, may be deposited to a thickness in a range from 40 Å to 100 Å. A portion of the electrically insulating liner is then removed from a bottom of the contact hole and a barrier metal layer is then formed on the electrically insulating liner and on a bottom of the contact hole. The step of forming the barrier metal layer may be followed by filling the contact hole with a metal interconnect.

摘要翻译： 形成集成电路器件的方法包括在衬底上形成其中具有接触孔的电绝缘层，然后使用原子层沉积（ALD）技术将电绝缘衬垫沉积到接触孔的侧壁上。 例如，可以包括凝胶状二氧化硅或二氧化硅的这种电绝缘衬垫可以沉积到从而在一个范围内的厚度。 然后从接触孔的底部去除电绝缘衬垫的一部分，然后在电绝缘衬垫上和接触孔的底部上形成阻挡金属层。 形成阻挡金属层的步骤之后可以用金属互连填充接触孔。

公开(公告)号：US07393746B2

公开(公告)日：2008-07-01

申请号：US11548870

申请日：2006-10-12

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee ,  JunJung Kim

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee ,  JunJung Kim

IPC分类号： H01L21/33

CPC分类号： H01L21/32 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

摘要翻译： 一种方法在衬底上形成栅极导体，在栅极导体的侧面上形成间隔物（例如，氮化物间隔物），并将杂质注入到未被栅极导体和间隔物保护的衬底的暴露区域中。 然后，该方法在衬底的暴露区域的表面上形成硅化物。 该方法在硅化物，间隔物和栅极导体之上形成共形保护层（例如，氧化物或其它类似材料）。 接下来，该方法在保护层上形成非共形牺牲层（例如，可相对于保护层选择性去除的氮化物或其它材料）。 随后的部分蚀刻工艺部分地蚀刻牺牲层，使得在间隔物之上的牺牲层的相对较薄的区域被完全去除，并且除去衬底之上的牺牲层的相对较厚的区域。 该方法中的下一步骤仅去除覆盖间隔物的保护层的那些部分，而不去除覆盖硅化物的保护层的部分。 由于间隔物现在被暴露并且硅化物被保护层和牺牲层保护，所以该方法可以安全地去除间隔物而不影响硅化物。

公开(公告)号：US20080054413A1

公开(公告)日：2008-03-06

申请号：US11468536

申请日：2006-08-30

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan

IPC分类号： H01L23/58 ,  H01L21/469

CPC分类号： H01L21/76829 ,  H01L21/823807 ,  H01L29/7843

摘要： A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.

摘要翻译： 提供一种形成覆盖第一组和第二组半导体器件的双段衬套的方法。 该方法包括在其顶部形成第一衬垫和第一保护层，第一衬套覆盖第一组半导体器件; 形成第二衬垫，所述第二衬套具有覆盖所述第一保护层的第一部分，过渡部分和覆盖所述第二组半导体器件的第二部分，所述第二部分经由所述过渡部分自对准到所述第一衬里; 在所述第二衬垫的所述第二部分的顶部上形成第二保护层; 移除所述第二衬套的所述第一部分和所述过渡部分的至少一部分; 并且获得包括第一衬套，第二衬套的过渡部分和第二部分的双段衬管。 还提供了根据本发明的一个实施例形成的具有自对准双段衬垫的半导体结构。

公开(公告)号：US07223691B2

公开(公告)日：2007-05-29

申请号：US10965031

申请日：2004-10-14

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888

摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

摘要翻译： 具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。 该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。 优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

公开(公告)号：US07220662B2

公开(公告)日：2007-05-22

申请号：US10905549

申请日：2005-01-10

申请人： Huilong Zhu ,  Sunfei Fang ,  Zhijiong Luo

发明人： Huilong Zhu ,  Sunfei Fang ,  Zhijiong Luo

IPC分类号： H01L21/3205

CPC分类号： H01L21/28097 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66545

摘要： Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.

摘要翻译： 通过避免常规的化学机械抛光步骤通过将侧壁蚀刻到硅来暴露硅栅来形成全硅化平面场效应晶体管; 在间隔物的栅极和侧壁的顶部上沉积牺牲氧化物层，但在S / D区域上较厚，在保护S / D的同时蚀刻氧化物以露出堆叠栅极的顶部; 凹陷硅; 剥离氧化物; 沉积金属和退火以在栅极和S / D上形成硅化物。

公开(公告)号：US20060154461A1

公开(公告)日：2006-07-13

申请号：US10905549

申请日：2005-01-10

申请人： Huilong Zhu ,  Sunfei Fang ,  Zhijiong Luo

发明人： Huilong Zhu ,  Sunfei Fang ,  Zhijiong Luo

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/28097 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66545

摘要： Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.

摘要翻译： 通过避免常规的化学机械抛光步骤通过将侧壁蚀刻到硅来暴露硅栅来形成全硅化平面场效应晶体管; 在间隔物的栅极和侧壁的顶部上沉积牺牲氧化物层，但在S / D区域上较厚，在保护S / D的同时蚀刻氧化物以露出堆叠栅极的顶部; 凹陷硅; 剥离氧化物; 沉积金属和退火以在栅极和S / D上形成硅化物。

公开(公告)号：US08629022B2

公开(公告)日：2014-01-14

申请号：US13420730

申请日：2012-03-15

申请人： Dureseti Chidambarrao ,  Sunfei Fang ,  Yue Liang ,  Xiaojun Yu ,  Jun Yuan

发明人： Dureseti Chidambarrao ,  Sunfei Fang ,  Yue Liang ,  Xiaojun Yu ,  Jun Yuan

IPC分类号： H01L21/8234

CPC分类号： H01L27/092 ,  H01L21/823857 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78

摘要： A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.

摘要翻译： 提供一种形成半导体结构的方法。 该方法包括提供包括位于半导体衬底的表面上的至少一个伪栅极区域和位于至少一个虚拟栅极区域的侧壁上的介电材料层的结构。 接下来，去除暴露下面的高k栅极电介质的虚拟栅极区域的一部分。 然后在高k栅极电介质的上表面上形成倾斜的阈值电压调节材料层，然后在倾斜的阈值电压调节材料层的顶部形成栅极导体。