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    Method of forming ultra-thin silicidation-stop extensions in mosfet devices
    1.
    发明授权
    Method of forming ultra-thin silicidation-stop extensions in mosfet devices 有权
    在mosfet器件中形成超薄硅化 - 停止延伸的方法

    公开(公告)号：US06989322B2

    公开(公告)日：2006-01-24

    申请号：US10707175

    申请日：2003-11-25

    申请人： Oleg G. Gluschenkov ,  Cyril Cabral, Jr. ,  Omer Dokumaci ,  Christian Lavoie

    发明人： Oleg G. Gluschenkov ,  Cyril Cabral, Jr. ,  Omer Dokumaci ,  Christian Lavoie

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/0847 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide and the channel.

    摘要翻译： 通过使用薄硅化停止扩展来形成MOSFET器件中的非常低的电阻，其既用作硅化“阻挡”势垒，又作为源/漏硅化物区域和MOSFET的沟道区之间的薄界面层。 通过作为硅化停止，硅化 - 停止扩展限制硅化，并且不被源/漏硅化物破坏。 这允许在硅化物和沟道之间形成非常薄的，高掺杂的硅化 - 停止延伸，在硅化物和沟道之间提供基本理想的低串联电阻接口。

    Implantless Dopant Segregation for Silicide Contacts
    3.
    发明申请
    Implantless Dopant Segregation for Silicide Contacts 有权
    用于硅胶接触的无植入物掺杂剂分离

    公开(公告)号：US20120009771A1

    公开(公告)日：2012-01-12

    申请号：US12833272

    申请日：2010-07-09

    申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

    发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

    摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

    摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

    Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby
    4.
    发明授权
    Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby 失效
    自对准金属与Ge形成的基板和由此形成的结构形成接触

    公开(公告)号：US07682968B2

    公开(公告)日：2010-03-23

    申请号：US12108001

    申请日：2008-04-23

    申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

    发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

    摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

    摘要翻译： 提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

    Retarding agglomeration of Ni monosilicide using Ni alloys
    5.
    发明授权
    Retarding agglomeration of Ni monosilicide using Ni alloys 有权
    使用Ni合金抑制Ni一硅化物的团聚

    公开(公告)号：US07271486B2

    公开(公告)日：2007-09-18

    申请号：US11075289

    申请日：2005-03-08

    申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  James M. E. Harper ,  Christian Lavoie

    发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  James M. E. Harper ,  Christian Lavoie

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： C04B35/58 ,  C04B35/58085 ,  C04B2235/40 ,  C04B2235/404 ,  C04B2235/405 ,  C04B2235/408 ,  C23C26/00 ,  C23C30/00 ,  H01L21/28518 ,  H01L21/76889

    摘要： A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.

    摘要翻译： 一种用于提供半导体器件中有用的低电阻非聚集Ni单硅化物接触的方法。 在制造基本上非团聚的Ni合金一硅化硅的本发明方法中，包括以下步骤：在含Si衬底的一部分上形成金属合金层，其中所述金属合金层包括Ni和一种或多种合金添加剂 ），其中所述合金添加剂为Ti，V，Ge，Cr，Zr，Nb，Mo，Hf，Ta，W，Re，Rh，Pd或Pt或其混合物; 在将所述金属合金层的一部分转化为Ni合金一硅化物层的温度下退火金属合金层; 并且除去未转化为Ni合金一硅化物的剩余金属合金层。 选择合金添加剂用于相稳定性并阻止团聚。 延迟聚集中最有效的合金添加剂在生产低薄层电阻的硅化物中是最有效的。

    Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi
    6.
    发明授权
    Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi 失效
    CoSi的预退火，以防止在Ti-O-N和CoSi之间形成非晶层

    公开(公告)号：US06878624B1

    公开(公告)日：2005-04-12

    申请号：US10674645

    申请日：2003-09-30

    申请人： John Bruley ,  Cyril Cabral, Jr. ,  Christian Lavoie ,  Tina J. Wagner ,  Yun Yu Wang ,  Horati S. Wildman ,  Wong Kwong Hon

    发明人： John Bruley ,  Cyril Cabral, Jr. ,  Christian Lavoie ,  Tina J. Wagner ,  Yun Yu Wang ,  Horati S. Wildman ,  Wong Kwong Hon

    IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52

    CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/76856 ,  H01L29/665

    摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

    摘要翻译： 本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。 本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。 氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。 因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

    Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed
    9.
    发明授权
    Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed 有权
    在半导体结构中的金属硅化物层的顶部上形成TiN层的方法和形成的结构

    公开(公告)号：US06436823B1

    公开(公告)日：2002-08-20

    申请号：US09679738

    申请日：2000-10-05

    申请人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

    发明人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

    IPC分类号： H01L2144

    CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L2221/1078

    摘要： A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

    摘要翻译： 提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法，而不形成含有Ti，Co和Si的厚非晶层以及形成的结构。 在该方法中，在金属硅化物层的顶部沉积Ti层之后，进行双相退火工艺，其中在不高于500℃的温度下在成形气体（或氨）中进行低温退火。 首先进行少于2小时，然后在不低于500℃的第二温度下在含氮气体（或氨）中进行低温退火2小时以形成TiN层。 本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题，并导致由于体积膨胀引起的衬管故障 无定形材料。 通过本发明方法形成的非晶材料层的最大厚度小于5nm，这使线路故障问题最小化。