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145 条记录 (耗时 0.032 秒)

    Immersion lithographic process using a conforming immersion medium
    62.
    发明授权
    Immersion lithographic process using a conforming immersion medium 失效
    浸渍光刻工艺使用一致的浸渍介质

    公开(公告)号：US07125652B2

    公开(公告)日：2006-10-24

    申请号：US10726413

    申请日：2003-12-03

    申请人： Christopher F. Lyons ,  Carl P. Babcock ,  Jongwook Kye

    发明人： Christopher F. Lyons ,  Carl P. Babcock ,  Jongwook Kye

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70341

    摘要： A method of making a device using a lithographic system having a lens from which an exposure pattern is emitted. A conforming immersion medium can be positioned between a photo resist layer and the lens. The photo resist layer, which can be disposed over a wafer, and the lens can be brought into intimate contact with the conforming immersion medium. The photo resist can then be exposed with the exposure pattern so that the exposure pattern traverses the conforming immersion medium.

    摘要翻译： 一种制造使用具有透镜的光刻系统的装置的方法，曝光图案从该透镜发射。 适配浸没介质可以位于光致抗蚀剂层和透镜之间。 可以设置在晶片上的光致抗蚀剂层，并且透镜可以与合适的浸渍介质紧密接触。 然后可以用曝光图案曝光光致抗蚀剂，使得曝光图案穿过合适的浸渍介质。

    Shallow trench isolation polish stop layer for reduced topography
    63.
    发明授权
    Shallow trench isolation polish stop layer for reduced topography 失效
    浅沟隔离抛光停止层减少地形

    公开(公告)号：US07056804B1

    公开(公告)日：2006-06-06

    申请号：US10790366

    申请日：2004-03-01

    申请人： Christopher F. Lyons ,  Ramkumar Subramanian

    发明人： Christopher F. Lyons ,  Ramkumar Subramanian

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： A method of making and shallow trench isolation feature including 1) providing a semiconductor substrate, 2) forming a polish stop layer over the semiconductor substrate, 3) forming a nitride containing layer over the polish stop layer, 4) forming a shallow trench layer through a portion of the nitride containing layer, a portion of the polish stop layer and a portion of the semiconductor substrate, 5) removing the nitride containing layer by a chemical mechanical polishing process, and 6) planarizing the shallow trench layer and the polish stop layer until a surface of the shallow trench layer and a surface of the polish stop layer are co-planar.

    摘要翻译： 一种制造和浅沟槽隔离特征的方法，包括1）提供半导体衬底，2）在半导体衬底上形成抛光停止层，3）在抛光停止层上形成含氮化物层，4）形成浅沟槽层， 含氮化物层的一部分，抛光停止层的一部分和半导体衬底的一部分，5）通过化学机械抛光工艺除去含氮化物层，以及6）使浅沟槽层和抛光停止层平坦化 直到浅沟槽层的表面和抛光停止层的表面是共面的。

    Metal bridging monitor for etch and CMP endpoint detection
    65.
    发明授权
    Metal bridging monitor for etch and CMP endpoint detection 失效
    用于蚀刻和CMP端点检测的金属桥接监视器

    公开(公告)号：US07011762B1

    公开(公告)日：2006-03-14

    申请号：US10419534

    申请日：2003-04-21

    申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Steven C. Avanzino

    发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Steven C. Avanzino

    IPC分类号： C23F1/00 ,  G01R31/00

    CPC分类号： H01L21/3212 ,  H01L21/32051 ,  H01L21/32136 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.

    摘要翻译： 本发明的一个方面涉及包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层和至少一个嵌入在晶片内和晶片中的至少一个的电传感器，以便于金属的实时监测 当它通过减色金属化过程进行时。 本发明的另一方面涉及一种用于实时监测减色金属化过程以便在持续过程中实现立即响应的系统和方法。 该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动 从电传感器检测和接收，用于实时监测减色金属化处理。

    Ion implantation to modulate amorphous carbon stress
    66.
    发明授权
    Ion implantation to modulate amorphous carbon stress 失效
    离子注入调节无定形碳应力

    公开(公告)号：US06989332B1

    公开(公告)日：2006-01-24

    申请号：US10217730

    申请日：2002-08-13

    申请人： Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Christopher F. Lyons

    发明人： Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Christopher F. Lyons

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  C23C16/26 ,  C23C16/56 ,  H01L21/0332

    摘要： A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.

    摘要翻译： 一种制造集成电路的方法包括在半导体衬底之上提供多晶硅材料层。 在多晶硅材料层上方提供无定形碳层，惰性离子注入到无定形碳层中。 将非晶碳层图案化以形成无定形碳掩模，并且根据无定形碳掩模在多晶硅层中形成特征。

    Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning
    69.
    发明授权
    Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning 失效
    选择性应力诱导植入物和无定形碳图案化导致的图案变形

    公开(公告)号：US06825114B1

    公开(公告)日：2004-11-30

    申请号：US10424675

    申请日：2003-04-28

    申请人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

    发明人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2144

    CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

    摘要翻译： 使用非晶碳掩模形成用于集成电路的熔丝的方法包括在导电层上提供包含无定形碳的掩模材料层。 掩模材料层掺杂有氮，并且在掩模层上形成抗反射涂层（ARC）特征。 根据ARC特征去除掩模材料层的一部分以形成掩模，并且去除ARC特征以形成翘曲的掩模。 根据翘曲的掩模对导电层进行图案化，去除翘曲的掩模，并且在图案化的导电层上提供硅化物层。