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    Isolation trench fill process
    3.
    发明授权
    Isolation trench fill process 有权
    隔离沟填充过程

    公开(公告)号：US06806165B1

    公开(公告)日：2004-10-19

    申请号：US10120116

    申请日：2002-04-09

    申请人： Dawn M. Hopper ,  Minh V. Ngo ,  Mark S. Chang

    发明人： Dawn M. Hopper ,  Minh V. Ngo ,  Mark S. Chang

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A method for filling an isolation trench structure during a semiconductor fabrication process is disclosed. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an oxide utilizing a biased high density plasma deposition process. In a preferred embodiment, the silicon-rich liner is an in-situ HDP liner having a thickness of between 100 and 400 Angstroms, and preferably 200 Angstroms. Depositing a silicon-rich liner on the trench surface prior to depositing the high density plasma oxide eliminates the formation of defects at the surface of the isolation trench structure. Thus, the quality of the oxide fill is improved, as is yield and device performance.

    摘要翻译： 公开了一种在半导体制造过程中填充隔离沟槽结构的方法。 该方法包括两步沉积工艺，其包括在沟槽表面上沉积富硅衬垫，然后用偏压的高密度等离子体沉积工艺用氧化物填充隔离沟槽。 在优选的实施方案中，富硅衬里是厚度为100至400埃，优选为200埃的原位HDP衬垫。 在沉积高密度等离子体氧化物之前，在沟槽表面上沉积富硅衬层消除了在隔离沟槽结构表面形成缺陷。 因此，提高了氧化物填充的质量，以及产量和器件性能。

    Method for Manufacturing a Surface Mount Device
    4.
    发明申请
    Method for Manufacturing a Surface Mount Device 有权
    表面贴装装置制造方法

    公开(公告)号：US20160104559A1

    公开(公告)日：2016-04-14

    申请号：US14513568

    申请日：2014-10-14

    申请人： Mario G. Sepulveda ,  Martin G. Pineda ,  Anthony Vranicar ,  Kedar V. Bhatawadekar ,  Minh V. Ngo ,  Dov Nitzan

    发明人： Mario G. Sepulveda ,  Martin G. Pineda ,  Anthony Vranicar ,  Kedar V. Bhatawadekar ,  Minh V. Ngo ,  Dov Nitzan

    IPC分类号： H01C17/00 ,  H01C1/034 ,  H01C7/02

    CPC分类号： H01C1/034 ,  H01C1/1406 ,  H01C7/001 ,  H01C17/02

    摘要： A method of manufacturing a surface mount device includes forming a plaque from a material, forming a plurality of conductive protrusions on a top surface and a bottom surface of the plaque, and applying a liquid encapsulant over at least a portion of the top surface and at least a portion of the bottom surface of the plaque. The liquid encapsulant is cured and when cured encapsulant has an oxygen permeability of less than about 0.4 cm3·mm/m2·atm·day. The assembly is cut to provide a plurality of components. After cutting, the top surface of each component includes at least one conductive protrusion, the bottom surface of each component includes at least one conductive protrusion, the top surface and the bottom surface of each component include the cured encapsulant, and a core of each component includes the material.

    摘要翻译： 一种制造表面贴装装置的方法包括从材料形成斑块，在板的顶表面和底表面上形成多个导电突起，以及在顶表面的至少一部分上以及 斑块底面的至少一部分。 液体密封剂固化，固化后的密封剂的氧气渗透率小于约0.4 cm3·mm / m2·atm·天。 组件被切割以提供多个部件。 在切割之后，每个部件的顶表面包括至少一个导电突起，每个部件的底表面包括至少一个导电突起，每个部件的顶表面和底表面包括固化的密封剂，以及每个部件的芯部 包括材料。

    Tensile strained substrate
    5.
    发明授权
    Tensile strained substrate 有权
    拉伸应变基材

    公开(公告)号：US07701019B2

    公开(公告)日：2010-04-20

    申请号：US11356606

    申请日：2006-02-17

    申请人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

    发明人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

    IPC分类号： H01L27/088

    CPC分类号： H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

    摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

    摘要翻译： 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

    Semiconductor with tensile strained substrate and method of making the same
    7.
    发明授权
    Semiconductor with tensile strained substrate and method of making the same 有权
    具有拉伸应变衬底的半导体及其制造方法

    公开(公告)号：US07001837B2

    公开(公告)日：2006-02-21

    申请号：US10346617

    申请日：2003-01-17

    申请人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

    发明人： Minh V. Ngo ,  Paul R. Besser ,  Ming Ren Lin ,  Haihong Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

    摘要： An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

    摘要翻译： 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

    Structure and method for preventing process-induced UV radiation damage in a memory cell
    8.
    发明授权
    Structure and method for preventing process-induced UV radiation damage in a memory cell 有权
    用于防止在存储器单元中的加工诱导的UV辐射损伤的结构和方法

    公开(公告)号：US06833581B1

    公开(公告)日：2004-12-21

    申请号：US10460282

    申请日：2003-06-12

    申请人： Angela Hui ,  Minh V. Ngo ,  Ning Cheng ,  Jaeyong Park ,  Jean Y. Yang ,  Kouros Ghandehari ,  Hirokazu Tokuno

    发明人： Angela Hui ,  Minh V. Ngo ,  Ning Cheng ,  Jaeyong Park ,  Jean Y. Yang ,  Kouros Ghandehari ,  Hirokazu Tokuno

    IPC分类号： H01L29788

    CPC分类号： H01L27/11568 ,  H01L23/556 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell and may include a gate situated over an ONO stack. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer situated directly over the interlayer dielectric layer, where the UV radiation blocking layer is selected from the group consisting of silicon-rich oxide and silicon-rich nitride. The UV radiation blocking layer may have a thickness of between approximately 1500.0 Angstroms and approximately 2000.0 Angstroms, for example.

    摘要翻译： 根据一个示例性实施例，一种结构包括基底。 该结构还包括位于基板上的至少一个存储单元。 至少一个存储器单元可以是例如闪速存储器单元，例如SONOS闪存单元，并且可以包括位于ONO堆栈上的门。 所述结构还包括位于所述至少一个存储器单元上方并位于所述衬底之上的层间电介质层。 根据该示例性实施例，该结构还包括直接位于层间电介质层上的UV辐射阻挡层，其中UV辐射阻挡层选自富硅氧化物和富含硅的氮化物。 例如，UV辐射阻挡层的厚度可以在约1500.0埃和约2000.0埃之间。