公开(公告)号：US09166567B2

公开(公告)日：2015-10-20

申请号：US14210892

申请日：2014-03-14

申请人： Bong Il Park ,  Andrew B. Kahng ,  Seok Hyeong Kang ,  Jae Gon Lee

发明人： Bong Il Park ,  Andrew B. Kahng ,  Seok Hyeong Kang ,  Jae Gon Lee

IPC分类号： G05F1/10 ,  G05F3/02 ,  H03K3/012 ,  H03K3/356

CPC分类号： H03K3/012 ,  H03K3/356008

摘要： A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.

摘要翻译： 提供电源门控电路及包括其的装置。 电源门控电路包括触发器，其被配置为接收第一电源电压和门控时钟信号以进行操作;以及开关电路，其连接在被配置为提供第一电源电压的第一电源电压源和第二电源电压 电压源被配置为提供第二电源电压。 开关电路包括第一开关，其被配置为连接在第一电源电压源和第二电源电压源之间并且响应于时钟使能信号而工作;第二开关被配置为连接在第一电源电压源 和第二电源电压源，并响应于第一电源电压而工作。

公开(公告)号：US07928020B2

公开(公告)日：2011-04-19

申请号：US11862865

申请日：2007-09-27

申请人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/00

CPC分类号： H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

摘要翻译： 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

公开(公告)号：US20080173934A1

公开(公告)日：2008-07-24

申请号：US12048994

申请日：2008-03-14

申请人： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

发明人： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

IPC分类号： H01L27/092

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.

摘要翻译： 一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

公开(公告)号：US20080087958A1

公开(公告)日：2008-04-17

申请号：US11951833

申请日：2007-12-06

申请人： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

发明人： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

IPC分类号： H01L27/088

CPC分类号： H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

摘要： A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

摘要翻译： 半导体器件提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

公开(公告)号：US20070090484A1

公开(公告)日：2007-04-26

申请号：US11162027

申请日：2005-08-25

申请人： Jae Gon Lee ,  Cher Sian Chua ,  Chew Hoe Ang ,  Liang-Choo Hsia

发明人： Jae Gon Lee ,  Cher Sian Chua ,  Chew Hoe Ang ,  Liang-Choo Hsia

IPC分类号： H01L29/00

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

摘要： An integrated circuit stress control system is provided. A gate is formed on a substrate and a channel is formed in the substrate. A source/drain is formed around the gate. A shallow trench isolation is formed in the substrate, the shallow trench isolation producing strain on the channel. A stress suppressing feature is formed in the substrate.

摘要翻译： 提供集成电路应力控制系统。 栅极形成在衬底上，并且沟道形成在衬底中。 源极/漏极围绕栅极形成。 在衬底中形成浅沟槽隔离，通道上的浅沟槽隔离产生应变。 在基板上形成应力抑制特征。

公开(公告)号：US20060252188A1

公开(公告)日：2006-11-09

申请号：US10908328

申请日：2005-05-06

申请人： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

发明人： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

摘要： A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

摘要翻译： 用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。