公开(公告)号：US08041537B2

公开(公告)日：2011-10-18

申请号：US12163081

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G04F1/00

CPC分类号： H03K5/1565

摘要： Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.

摘要翻译： 本公开的实施例提供了用于时钟占空比测量的系统和方法。 时钟信号和时钟信号的补码在第一和第二预定定时窗口期间提供给电荷泵。 电荷泵可操作以分别在第一和第二定时窗口期间响应于时钟信号和时钟信号的补码产生第一和第二输出电压。 此外，预定的正电压和接地电压分别在预定的第三和第四定时窗口期间施加到电荷泵。 电荷泵可操作以分别在第三和第四定时窗口期间产生对应于预定正电压和接地电压的第三和第四输出电压信号。 然后，使用第一，第二，第三和第四电压来计算时钟的占空比。

公开(公告)号：US07969250B2

公开(公告)日：2011-06-28

申请号：US12129811

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03B27/00

CPC分类号： H03L7/183 ,  H03L7/0998

摘要： A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

摘要翻译： 提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）的设计结构。 利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。 从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。 通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

公开(公告)号：US07917318B2

公开(公告)日：2011-03-29

申请号：US12129980

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

IPC分类号： G01R13/00

CPC分类号： H03K5/1565 ,  G01R31/31727

摘要： A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

摘要翻译： 提供了用于测量集成电路装置上任何地方的信号的绝对占空比的电路的设计结构。 该电路具有多个基本上相同的脉冲整形器元件，每个脉冲整形器元件使占空比要被测量相同量的输入信号的脉冲扩展。 脉冲整形器元件的输出可以耦合到基本相同的分频器电路，其输出耦合到多路复用器，其选择两个输入以输出到一组主/从配置的触发器，一个输入用作时钟，另一个作为时钟，另一个作为 数据到触发器。 触发器对由多路复用器选择的分频器输出进行采样，以检测分频器是否发生故障。 触发器的输出被提供给异或门，其输出表示输入信号的占空比的占空比信号。

公开(公告)号：US07895005B2

公开(公告)日：2011-02-22

申请号：US11942966

申请日：2007-11-20

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

IPC分类号： G01R13/00

CPC分类号： G01R29/02 ,  G01R31/31725

摘要： A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

摘要翻译： 提供了用于测量集成电路设备上任何地方的信号的绝对占空比的机制。 该机构采用具有多个基本相同的脉冲整形器元件的电路，每个脉冲整形器元件的占空比将被测量相同量的输入信号的脉冲。 脉冲整形器元件的输出可以耦合到基本相同的分频器电路，其输出耦合到多路复用器，其选择两个输入以输出到一组主/从配置的触发器，一个输入用作时钟，另一个作为时钟，另一个作为 数据到触发器。 触发器对由多路复用器选择的分频器输出进行采样，以检测分频器是否发生故障。 触发器的输出被提供给异或门，其输出表示输入信号的占空比的占空比信号。

公开(公告)号：US07831006B2

公开(公告)日：2010-11-09

申请号：US12132871

申请日：2008-06-04

申请人： David William Boerstler ,  Eskinder Hailu ,  Mack Wayne Riley ,  Michael Fan Wang

发明人： David William Boerstler ,  Eskinder Hailu ,  Mack Wayne Riley ,  Michael Fan Wang

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H03K23/662 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： An apparatus is provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

摘要翻译： 提供了一种用于减少模式转换期间的瞬态电流摆动的装置。 传统上，芯片上的瞬态电源电压波动占大部分电源。 串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。 然而，不能实现串联电感和电阻的降低的情况。 因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

公开(公告)号：US07646177B2

公开(公告)日：2010-01-12

申请号：US12347853

申请日：2008-12-31

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H02J7/00

CPC分类号： G01R31/31727

摘要： A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit may apply a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. The design structure may specify that control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

摘要翻译： 用于片上占空比测量系统的设计结构可以体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构可以体现测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比的装置。 设计结构可以指定DCM电路包括由电荷泵驱动的电容器，并且参考时钟信号驱动电荷泵。 设计结构可以指定时钟电路在多个已知占空比值之间改变参考时钟信号的占空比。 该设计结构可以指定DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路可以通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号的占空比的新电压值。 设计结构可以指定控制软件访问数据存储以确定测试时钟信号对应的占空比。

公开(公告)号：US20090322311A1

公开(公告)日：2009-12-31

申请号：US12163166

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G01R23/02 ,  G06F1/04

CPC分类号： G06F1/08

摘要： Embodiments of the disclosure provide systems and methods for using a PLL and a high frequency generator outside the loop to obtain the fmax of the divider. The divider in the PLL loop is fed by a VCO and its operation range is characterized by measuring the PLL lock range. An identical copy of the same divider is used outside the PLL loop and it is fed by a higher frequency clock. The high frequency clock is generated by the multiple phase of the VCO. By characterizing the outputs from both dividers, the fmax of the divider is obtained.

摘要翻译： 本公开的实施例提供了在环路外部使用PLL和高频发生器以获得分频器的fmax的系统和方法。 PLL环路中的分频器由VCO馈送，其工作范围的特征在于测量PLL锁定范围。 相同分频器的相同拷贝在PLL环路外部使用，并由较高频率的时钟馈送。 高频时钟由VCO的多相产生。 通过对来自两个分频器的输出进行表征，获得分频器的fmax。

公开(公告)号：US07620126B2

公开(公告)日：2009-11-17

申请号：US11236658

申请日：2005-09-27

申请人： David William Boerstler ,  Matthew E. Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Wayne Riley

发明人： David William Boerstler ,  Matthew E. Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Wayne Riley

IPC分类号： H03D3/18

CPC分类号： H03L7/093 ,  H03L7/095

摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

摘要翻译： 公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

公开(公告)号：US20090183136A1

公开(公告)日：2009-07-16

申请号：US12129811

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： G06F17/50

CPC分类号： H03L7/183 ,  H03L7/0998

摘要： A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

摘要翻译： 提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）的设计结构。 利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。 从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。 通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

公开(公告)号：US20090125262A1

公开(公告)日：2009-05-14

申请号：US11938456

申请日：2007-11-12

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

IPC分类号： G01R29/00

CPC分类号： G01R31/31727 ,  G01R29/0273 ,  H03K5/1565

摘要： A method and apparatus for measuring the absolute duty cycle of a signal are provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.

摘要翻译： 提供了用于测量信号的绝对占空比的方法和装置。 选择来自信号源的非反相路径，并循环各种DCC电路设置索引，直到耦合到DCC电路的输出的分频器失效。 然后，基于故障时的DCC电路的指标值来确定分路器故障时的第一最小脉冲宽度。 选择来自信号源的反向路径，并且各种DCC电路设置索引再次循环，直到分频器失效。 然后，基于该第二次故障时的DCC电路的指标值来确定分路器故障时的第二最小脉冲宽度。 然后基于第一和第二最小脉冲宽度值的差来计算占空比。