公开(公告)号：US20090326862A1

公开(公告)日：2009-12-31

申请号：US12163081

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G04F1/00 ,  H03L7/06

CPC分类号： H03K5/1565

摘要： Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.

摘要翻译： 本公开的实施例提供了用于时钟占空比测量的系统和方法。 时钟信号和时钟信号的补码在第一和第二预定定时窗口期间提供给电荷泵。 电荷泵可操作以分别在第一和第二定时窗口期间响应于时钟信号和时钟信号的补码产生第一和第二输出电压。 此外，预定的正电压和接地电压分别在预定的第三和第四定时窗口期间施加到电荷泵。 电荷泵可操作以分别在第三和第四定时窗口期间产生对应于预定正电压和接地电压的第三和第四输出电压信号。 然后，使用第一，第二，第三和第四电压来计算时钟的占空比。

公开(公告)号：US08041537B2

公开(公告)日：2011-10-18

申请号：US12163081

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G04F1/00

CPC分类号： H03K5/1565

摘要： Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.

摘要翻译： 本公开的实施例提供了用于时钟占空比测量的系统和方法。 时钟信号和时钟信号的补码在第一和第二预定定时窗口期间提供给电荷泵。 电荷泵可操作以分别在第一和第二定时窗口期间响应于时钟信号和时钟信号的补码产生第一和第二输出电压。 此外，预定的正电压和接地电压分别在预定的第三和第四定时窗口期间施加到电荷泵。 电荷泵可操作以分别在第三和第四定时窗口期间产生对应于预定正电压和接地电压的第三和第四输出电压信号。 然后，使用第一，第二，第三和第四电压来计算时钟的占空比。

公开(公告)号：US20090322311A1

公开(公告)日：2009-12-31

申请号：US12163166

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G01R23/02 ,  G06F1/04

CPC分类号： G06F1/08

摘要： Embodiments of the disclosure provide systems and methods for using a PLL and a high frequency generator outside the loop to obtain the fmax of the divider. The divider in the PLL loop is fed by a VCO and its operation range is characterized by measuring the PLL lock range. An identical copy of the same divider is used outside the PLL loop and it is fed by a higher frequency clock. The high frequency clock is generated by the multiple phase of the VCO. By characterizing the outputs from both dividers, the fmax of the divider is obtained.

摘要翻译： 本公开的实施例提供了在环路外部使用PLL和高频发生器以获得分频器的fmax的系统和方法。 PLL环路中的分频器由VCO馈送，其工作范围的特征在于测量PLL锁定范围。 相同分频器的相同拷贝在PLL环路外部使用，并由较高频率的时钟馈送。 高频时钟由VCO的多相产生。 通过对来自两个分频器的输出进行表征，获得分频器的fmax。

公开(公告)号：US20090132971A1

公开(公告)日：2009-05-21

申请号：US12130040

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03B19/00 ,  G06F17/50

CPC分类号： G06F17/5045 ,  H03K3/017 ,  H03L7/0995 ,  H03L2207/06

摘要： A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

摘要翻译： 提供了一种用于在没有预定标器的情况下获得期望的锁相环（PLL）占空比的电路的设计结构。 说明性实施例的PLL电路利用在VCO上同时工作的两个单独的环路。 一个环路确保频率和相位锁定，而另一个环路确保占空比锁定。 VCO被修改为具有附加的控制端口来调整占空比。 因此，VCO具有用于执行频率调整的一个控制端口和用于占空比调整的一个控制端口。 结果，可以使用说明性实施例的PLL电路的VCO来控制占空比和频率，以便实现任何期望的占空比输出，而不需要VCO预定标器电路或占空比校正电路。

公开(公告)号：US07511554B2

公开(公告)日：2009-03-31

申请号：US11764262

申请日：2007-06-18

申请人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03L5/00

CPC分类号： H03K19/01812 ,  H03K19/01831

摘要： Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

摘要翻译： 在具有不同电源电压的域中的集成电路（IC）组件之间传送信号的系统和方法。 AC耦合用于增加信号的共模电压从一个电平转移到另一个电平的速度。 一个实施例包括用于电平移位IC中的二进制信号的方法。 该方法包括接收输入二进制信号并将其AC分量与其共模分量去耦。 第二共模分量被添加到AC分量，提供二进制输出信号。 输入信号的共模电压可以大于（或更小）输出信号的共模电压。 在该方法的一个实施例中，执行占空比补偿（DCC）。 DCC将占空比驱动到所需的值。

公开(公告)号：US20090146743A1

公开(公告)日：2009-06-11

申请号：US11952706

申请日：2007-12-07

申请人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03L7/085 ,  H03L7/08

CPC分类号： H03L7/08

摘要： Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.

摘要翻译： 用于确定锁相环电路（PLL）中的压控振荡器（VCO）线性度，占空比确定和占空比校正的系统和方法一个实施例包括一种方法，包括以下步骤：将PLL的VCO的频率响应确定为 占空比的功能，将基于VCO输出的信号施加到VCO输入，测量VCO输出信号的最终频率，确定对应于测量频率的占空比，以及配置占空比校正单元校正占空比 的VCO输出信号约为50％。 确定VCO的频率响应可以包括对于0％和100％之间的几个不同占空比值的每一个，将VCO输入信号施加到VCO并确定VCO输出信号的对应频率。 这也可以在0％和100％的占空比下完成。

公开(公告)号：US20090128206A1

公开(公告)日：2009-05-21

申请号：US11942983

申请日：2007-11-20

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03K5/04 ,  H03L7/099

CPC分类号： H03K3/017 ,  H03L7/0995

摘要： An apparatus and method for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler are provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

摘要翻译： 提供了一种用于在没有预定标器的情况下获得期望的锁相环（PLL）占空比的装置和方法。 说明性实施例的PLL电路利用在VCO上同时工作的两个单独的环路。 一个环路确保频率和相位锁定，而另一个环路确保占空比锁定。 VCO被修改为具有附加的控制端口来调整占空比。 因此，VCO具有用于执行频率调整的一个控制端口和用于占空比调整的一个控制端口。 结果，可以使用说明性实施例的PLL电路的VCO来控制占空比和频率，以便实现任何期望的占空比输出，而不需要VCO预定标器电路或占空比校正电路。

公开(公告)号：US20090066424A1

公开(公告)日：2009-03-12

申请号：US11853905

申请日：2007-09-12

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03L7/00

CPC分类号： H03L7/18 ,  H03L7/0998

摘要： A programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. With the VCO, programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

摘要翻译： 提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）。 利用VCO，可以利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。 从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。 通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

公开(公告)号：US07969250B2

公开(公告)日：2011-06-28

申请号：US12129811

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03B27/00

CPC分类号： H03L7/183 ,  H03L7/0998

摘要： A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

摘要翻译： 提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）的设计结构。 利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。 从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。 通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

公开(公告)号：US07917318B2

公开(公告)日：2011-03-29

申请号：US12129980

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi ,  Bin Wan

IPC分类号： G01R13/00

CPC分类号： H03K5/1565 ,  G01R31/31727

摘要： A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

摘要翻译： 提供了用于测量集成电路装置上任何地方的信号的绝对占空比的电路的设计结构。 该电路具有多个基本上相同的脉冲整形器元件，每个脉冲整形器元件使占空比要被测量相同量的输入信号的脉冲扩展。 脉冲整形器元件的输出可以耦合到基本相同的分频器电路，其输出耦合到多路复用器，其选择两个输入以输出到一组主/从配置的触发器，一个输入用作时钟，另一个作为时钟，另一个作为 数据到触发器。 触发器对由多路复用器选择的分频器输出进行采样，以检测分频器是否发生故障。 触发器的输出被提供给异或门，其输出表示输入信号的占空比的占空比信号。