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    Dual poly deposition and through gate oxide implants
    61.
    发明授权
    Dual poly deposition and through gate oxide implants 有权
    双重聚合沉积和通过栅极氧化物植入

    公开(公告)号：US07435638B2

    公开(公告)日：2008-10-14

    申请号：US11441980

    申请日：2006-05-26

    申请人： Shaofeng Yu ,  Shyh-Horng Yang

    发明人： Shaofeng Yu ,  Shyh-Horng Yang

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823892 ,  H01L21/823842 ,  H01L21/823857

    摘要： Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.

    摘要翻译： 掺杂剂通过栅极电极材料和栅极电介质层的薄层以相对高的能量注入到半导体衬底的未屏蔽的第一区域中。 然后将较低能量的掺杂剂注入到栅极电极材料的薄层中。 然后掩蔽第一区域，并且该过程在半导体衬底的先前掩蔽的但现在未掩模的第二区域中重复。 然后在栅电极材料的薄层上形成第二（通常较厚）的栅电极材料层。 将厚栅极电极材料层，薄栅电极材料层和栅极电介质材料层图案化以在衬底的掺杂区域上形成一个或多个栅极结构。 源极和漏极区域形成在与栅极结构相邻的衬底区域中以建立一个或多个MOS晶体管。

    FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN
    62.
    发明申请
    FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN 有权
    具有完全硅化物电极和通道应变的晶体管的制造

    公开(公告)号：US20080191289A1

    公开(公告)日：2008-08-14

    申请号：US11674902

    申请日：2007-02-14

    申请人： Michael Francis Pas ,  Shaofeng Yu

    发明人： Michael Francis Pas ,  Shaofeng Yu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/28097 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

    摘要： Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.

    摘要翻译： 通过形成第一和第二栅极制造半导体器件，包括在衬底上图案化含硅层。 同时蚀刻第一栅极的图案化含硅层，以及与第一栅极相邻的第一衬底部分，以形成第一栅极电极和源极和漏极开口。 在第一栅极电极源极和漏极开口中同时形成SiGe。 第二栅极和第二衬底部分被掩蔽。 SiGe从第一浇口的上表面移除以在其中形成第二开口。 沉积在第一和第二栅极上的金属在其上形成金属层。 退火第一和第二浇口形成FUSI第一和第二栅电极。 在FUSI栅极电极层和底层栅极电介质层的界面处的金属量大于第二FUSI栅极电极层和下面的第二栅极电介质层的第二界面处的金属量。

    Dual poly deposition and through gate oxide implants
    63.
    发明申请
    Dual poly deposition and through gate oxide implants 有权
    双重聚合沉积和通过栅极氧化物植入

    公开(公告)号：US20070275517A1

    公开(公告)日：2007-11-29

    申请号：US11441980

    申请日：2006-05-26

    申请人： Shaofeng Yu ,  Shyh-Horng Yang

    发明人： Shaofeng Yu ,  Shyh-Horng Yang

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823892 ,  H01L21/823842 ,  H01L21/823857

    摘要： Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.

    摘要翻译： 掺杂剂通过栅极电极材料和栅极电介质层的薄层以相对高的能量注入到半导体衬底的未屏蔽的第一区域中。 然后将较低能量的掺杂剂注入到栅极电极材料的薄层中。 然后掩蔽第一区域，并且该过程在半导体衬底的先前掩蔽的但现在未掩模的第二区域中重复。 然后在栅电极材料的薄层上形成第二（通常较厚）的栅电极材料层。 将厚栅极电极材料层，薄栅电极材料层和栅极电介质材料层图案化以在衬底的掺杂区域上形成一个或多个栅极结构。 源极和漏极区域形成在与栅极结构相邻的衬底区域中以建立一个或多个MOS晶体管。