公开(公告)号：US20060179241A1

公开(公告)日：2006-08-10

申请号：US11054886

申请日：2005-02-10

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

IPC分类号： G06F13/28

CPC分类号： G06F12/0844 ,  G06F12/0817 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

摘要翻译： 高速缓存一致数据处理系统至少包括耦合用于通信的第一和第二相干域。 第一和第二相关域各自包括第一和第二高速缓存存储器中的相应一个。 第一相关域中的主机至少部分地基于类型，从包括第一相关域的第一范围和包括第一和第二相干域两者的第二范围中选择操作的初始广播的范围 的操作。 然后，主机使用所选择的范围在高速缓存相干数据处理系统内执行操作的初始广播。

公开(公告)号：US20060179223A1

公开(公告)日：2006-08-10

申请号：US11054930

申请日：2005-02-10

申请人： Leo Clark ,  Guy Guthrie ,  Kirk Livingston ,  William Starke

发明人： Leo Clark ,  Guy Guthrie ,  Kirk Livingston ,  William Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0822 ,  G06F12/0824

摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.

摘要翻译： 缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行 。 优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。 在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中 并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。 可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。 给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。 例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个 四个周期。

公开(公告)号：US20050251623A1

公开(公告)日：2005-11-10

申请号：US10825189

申请日：2004-04-15

申请人： Ravi Arimilli ,  Guy Guthrie ,  Hugh Shen ,  Derek Williams

发明人： Ravi Arimilli ,  Guy Guthrie ,  Hugh Shen ,  Derek Williams

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0804

摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.

摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。

公开(公告)号：US20070088926A1

公开(公告)日：2007-04-19

申请号：US11250022

申请日：2005-10-13

申请人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

IPC分类号： G06F12/14

CPC分类号： G06F12/0831 ,  G06F12/0815 ,  G06F12/0824

摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.

摘要翻译： 数据处理系统包括多个请求者和用于系统存储器的存储器控​​制器。 响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示 存储器控制器将该存储器块发送给请求者。 在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。 响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。

公开(公告)号：US20070033345A1

公开(公告)日：2007-02-08

申请号：US11195021

申请日：2005-08-02

申请人： Guy Guthrie ,  Derek Williams

发明人： Guy Guthrie ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851

摘要： A processing unit for a multiprocessor data processing system includes a processor core and a lower level cache including a reservation logic that records reservations of the processor core. The reservation logic passes or fails store-conditional operations received from the processor core based upon whether the processor core has reservations for target store addresses of the store-conditional operations. The processor core includes a store-through upper level cache, a reservation register, and sequencer logic that, by reference to the reservation register, fails a store-conditional operation without communication with said reservation logic.

摘要翻译： 一种用于多处理器数据处理系统的处理单元包括处理器核心和包含记录处理器核心预约的预约逻辑的下级高速缓存。 基于处理器核心是否具有对存储条件操作的目标存储地址的预留，预留逻辑通过或失败从处理器核心接收的存储条件操作。 处理器核心包括通过存储的上级缓存，预约寄存器和定序器逻辑，其通过参考预约寄存器而失败存储条件操作，而不与所述预留逻辑通信。

公开(公告)号：US20060090035A1

公开(公告)日：2006-04-27

申请号：US10970437

申请日：2004-10-21

申请人： Guy Guthrie ,  Hugh Shen ,  Derek Williams

发明人： Guy Guthrie ,  Hugh Shen ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3851

摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.

公开(公告)号：US20080040557A1

公开(公告)日：2008-02-14

申请号：US11836207

申请日：2007-08-09

申请人： Sanjeev Ghai ,  Guy Guthrie ,  John Hollaway

发明人： Sanjeev Ghai ,  Guy Guthrie ,  John Hollaway

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory.

摘要翻译： 数据处理系统包括系统存储器的存储器控​​制器，其接收指定相同地址的第一和第二突变操作。 响应于接收到所述第一和第二停顿操作，存储器控制器对系统存储器执行单次更新。

公开(公告)号：US20060179242A1

公开(公告)日：2006-08-10

申请号：US11054888

申请日：2005-02-10

申请人： Sanjeev Ghai ,  Guy Guthrie ,  John Hollaway

发明人： Sanjeev Ghai ,  Guy Guthrie ,  John Hollaway

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory.

摘要翻译： 数据处理系统包括系统存储器的存储器控​​制器，其接收指定相同地址的第一和第二突变操作。 响应于接收到所述第一和第二停顿操作，存储器控制器对系统存储器执行单次更新。

公开(公告)号：US20050251660A1

公开(公告)日：2005-11-10

申请号：US10840560

申请日：2004-05-06

申请人： Robert Bell ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  Jeffrey Stuecheli

发明人： Robert Bell ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  Jeffrey Stuecheli

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3824 ,  G06F9/3861

摘要： A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.

摘要翻译： 一种方法和处理器芯片设计，用于使得处理器核心能够在核心接收到存储队列已满的指示之后继续向商店队列发送存储操作。 处理器核心配置有推测存储逻辑，使得处理器核心能够在存储队列满信号被断言的同时继续发出存储操作。 投机发行的存储操作的副本放置在推测性存储缓冲区内。 核心等待来自存储队列的信号，指示存储操作被接受到存储队列中。 当存储队列中接受推测发出的存储操作时，该副本将从缓冲区中丢弃。 然而，当存储操作被拒绝时，推测存储逻辑在正常存储操作之前重新发布存储操作。

公开(公告)号：US20050193174A1

公开(公告)日：2005-09-01

申请号：US11041711

申请日：2005-01-22

申请人： Ravi Arimilli ,  Vicente Chung ,  Guy Guthrie ,  Jody Joyner

发明人： Ravi Arimilli ,  Vicente Chung ,  Guy Guthrie ,  Jody Joyner

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0831

摘要： A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference. One preference order is selected and the data is then retrieved from a cache line of the cache in the order selected.

摘要翻译： 一种用于向处理器通知所选择的数据传输顺序的处理器的方法。 该方法包括以下步骤：将系统组件经由数据总线耦合到处理器以实现数据传输，在系统组件逻辑处确定将数据发送到处理器的顺序，以及向数据总线发出与 数据，其中所选择的订单位向处理器提醒订单，并且以该顺序传送数据。 在优选实施例中，系统组件是高速缓存，并且该方法可以涉及在高速缓存处接收对来自处理器的读取地址/请求的排序的偏好。 高速缓存控制器或偏好顺序逻辑组件的偏好顺序逻辑通过将处理器偏好与其他偏好（包括高速缓存顺序偏好）进行比较来评估期望的顺序的偏好。 选择一个偏好顺序，然后以所选顺序从高速缓存的高速缓存行检索数据。