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61.发明申请Processor, Data Processing System and Method Supporting a Shared Global Coherency State 失效处理器，数据处理系统和支持共享全局一致性状态的方法公开(公告)号：US20080086602A1
公开(公告)日：2008-04-10
申请号：US11539694
申请日：2006-10-09
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. According to a method of data processing, a cache line is buffered in a data array of the cache memory and a state field in a cache directory of the cache memory is set to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in said second coherency domain may hold a copy of the cache line.
摘要翻译： 多处理器数据处理系统至少包括第一和第二相干域，其中第一相干域包括系统存储器和高速缓冲存储器。 根据数据处理的方法，将高速缓存行缓冲在高速缓冲存储器的数据阵列中，高速缓冲存储器的高速缓存目录中的状态字段被设置为一致性状态，以指示高速缓存行在数据中是有效的 数组，高速缓存存储器行被非排他地保存在高速缓冲存储器中，并且所述第二相干域中的另一个高速缓冲存储器可以保存高速缓存行的副本。
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62.发明授权Barriers processing in a multiprocessor system having a weakly ordered storage architecture without broadcast of a synchronizing operation 失效在具有弱排序存储体系结构的多处理器系统中进行障碍处理，而无需广播同步操作公开(公告)号：US08095739B2
公开(公告)日：2012-01-10
申请号：US12422698
申请日：2009-04-13
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0815 , G06F12/0862 , G06F12/126
摘要： A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. A request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete.
摘要翻译： 采用弱有序存储架构的数据处理系统包括彼此耦合的第一和第二组处理单元以及互连结构的数据存储。 每个处理单元具有处理器核心，其具有包括至少一级，二级和三级高速缓冲存储器的相关联的高速缓存层级。 在最后一个杀死型命令时，对包含在第一处理单元的三级高速缓冲存储器中的存储器的第一图像的一部分进行更新的请求在第一处理单元处于等待状态，第一处理的高速缓存层级 单元允许仅在至少一个杀死型命令完成之后将更新暴露给任何第一处理器核。
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63.发明申请Barriers Processing in a Multiprocessor System Having a Weakly Ordered Storage Architecture Without Broadcast of a Synchronizing Operation 失效具有弱序列存储架构的多处理器系统中的障碍处理，无需广播同步操作公开(公告)号：US20100262786A1
公开(公告)日：2010-10-14
申请号：US12422698
申请日：2009-04-13
CPC分类号： G06F12/0897 , G06F12/0815 , G06F12/0862 , G06F12/126
摘要： A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. In response to a request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete.
摘要翻译： 采用弱有序存储架构的数据处理系统包括彼此耦合的第一和第二组处理单元以及互连结构的数据存储。 每个处理单元具有处理器核心，其具有包括至少一级，二级和三级高速缓冲存储器的相关联的高速缓存层级。 响应于对包含在第一处理单元的三级高速缓冲存储器中的存储器的第一图像的一部分执行更新的请求，而最后一个杀死型命令在第一处理单元处于等待状态，则高速缓存层级 所述第一处理单元仅在所述至少一个杀死型命令完成之后允许所述更新暴露于任何第一处理器核心。
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公开(公告)号：US08645640B2
公开(公告)日：2014-02-04
申请号：US13166054
申请日：2011-06-22
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。 该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。 存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。
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65.发明授权Method and apparatus for performing data prefetch in a multiprocessor system 失效在多处理器系统中执行数据预取的方法和装置公开(公告)号：US08161245B2
公开(公告)日：2012-04-17
申请号：US11054173
申请日：2005-02-09
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0831 , G06F12/0851
摘要： A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.
摘要翻译： 公开了一种用于在多处理器系统中执行数据预取的方法和装置。 多处理器系统包括多个处理器，每个具有高速缓冲存储器。 缓存存储器被细分成多个片段。 一组预取请求最初由多处理器系统中的请求处理器发出。 每个预取请求用于请求处理器的高速缓冲存储器的相应片段之一。 响应于在请求处理器的高速缓冲存储器中错过的预取请求，预取请求被合并成一个组合预取请求。 然后将组合的预取请求发送到多处理器系统内的所有不请求处理器的高速缓冲存储器。 响应于来自所有非请求处理器的高速缓冲存储器的组合清洁响应，然后从系统存储器获得用于组合预取请求的数据。
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公开(公告)号：US08683160B2
公开(公告)日：2014-03-25
申请号：US13165982
申请日：2011-06-22
IPC分类号： G06F12/00
CPC分类号： G06Q50/10 , G06F12/0897
摘要： An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供存储器能量记帐的装置。 该装置包括系统存储器，存储器访问收集模块，存储器调节计数器和存储器信用计费模块。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓冲存储器的第一和第二组信号提取的高速缓存访问的结果跟踪每个用户的系统存储器的使用情况。
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公开(公告)号：US08650367B2
公开(公告)日：2014-02-11
申请号：US13585268
申请日：2012-08-14
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory A. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory A. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
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公开(公告)号：US10235215B2
公开(公告)日：2019-03-19
申请号：US12024169
申请日：2008-02-01
摘要： A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.
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公开(公告)号：US08205136B2
公开(公告)日：2012-06-19
申请号：US12189808
申请日：2008-08-12
IPC分类号： G11C29/00
CPC分类号： G11C29/832 , G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.
摘要翻译： 一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段 ，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员 的目录成员中的卡住位。 多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码 。 还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。
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公开(公告)号：US20100257317A1
公开(公告)日：2010-10-07
申请号：US12419364
申请日：2009-04-07
CPC分类号： G06F12/0811 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
摘要翻译： 数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元， 访问系统内存的虚拟屏障同步区域。 多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括从系统存储器的虚拟屏障同步区域缓存VBSR行的缓存阵列和高速缓存控制器。 高速缓存控制器响应于来自处理器核心的存储请求来更新特定VBSR线路，通过发送来同时保存特定VBSR线路的副本的多个处理单元中的彼此之间的高速缓存阵列的非阻塞更新 互连结构上的VBSR更新命令。
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