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公开(公告)号：US08205136B2
公开(公告)日：2012-06-19
申请号：US12189808
申请日：2008-08-12
IPC分类号： G11C29/00
CPC分类号： G11C29/832 , G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.
摘要翻译： 一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段 ，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员 的目录成员中的卡住位。 多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码 。 还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。
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公开(公告)号：US07689891B2
公开(公告)日：2010-03-30
申请号：US11225640
申请日：2005-09-13
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory which detects an error in a stored tag having an address field, a state field and an error-correction field, determines that the error is associated with a stuck bit of the directory member, marks the directory member as defective, and casts out corrected address information. The error is detected during processing of a cache directory access request, and is determined to be associated with a stuck bit of the directory member by attempting to correct a first error and then detecting a second error after the first correction attempt. The address information is cast out by routing a surrogate tag contained in a surrogate member of the cache directory through error-correction pipeline circuitry while transmitting the address information from the surrogate member to a cast-out machine.
摘要翻译： 一种处理高速缓冲存储器的目录中的卡住位的方法，该高速缓冲存储器的目录中检测到具有地址字段，状态字段和纠错字段的存储标签中的错误，确定该错误与该目录的卡住位相关联 会员，将目录成员标记为有缺陷，并丢弃修正的地址信息。 在处理高速缓存目录访问请求期间检测到错误，并且通过尝试校正第一错误然后在第一次校正尝试之后检测第二错误来确定与目录成员的卡住位相关联。 通过错误校正流水线电路路由包含在高速缓存目录的代理成员中的代理标签，同时将地址信息从代理成员发送到投放机器，来丢弃地址信息。
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公开(公告)号：US07533321B2
公开(公告)日：2009-05-12
申请号：US11225570
申请日：2005-09-13
IPC分类号： G11C29/00
CPC分类号： G11C29/832 , G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.
摘要翻译： 一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段 ，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员 的目录成员中的卡住位。 多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码 。 还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。
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4.发明授权Pipelining D states for MRU steerage during MRU-LRU member allocation 有权在MRU-LRU成员分配过程中管理D状态用于MRU操纵公开(公告)号：US07831774B2
公开(公告)日：2010-11-09
申请号：US12118238
申请日：2008-05-09
CPC分类号： G06F12/0888 , G06F12/123 , G06F12/126 , G06F2212/1032
摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
摘要翻译： 用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。 在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。 删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。 信息被锁存，然后传递给MRU向量生成逻辑。 生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。 使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。
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公开(公告)号：US20080301531A1
公开(公告)日：2008-12-04
申请号：US12189808
申请日：2008-08-12
CPC分类号： G11C29/832 , G06F11/1064
摘要： A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit.
摘要翻译： 一种通过定义多个二进制编码来指示缺陷高速缓存状态来处理高速缓冲存储器的目录中的卡住位的方法，检测存储在目录成员中的标签中的错误（其中标签至少包括地址字段 ，状态字段和纠错字段），确定错误与目录成员的卡住位相关联，并且基于字段位置将新状态信息写入从二进制编码之一中选择的目录成员 的目录成员中的卡住位。 多个二进制编码可以包括当卡住位在地址字段中时的第一二进制编码，当卡位位于状态字段时的第二二进制编码，以及当卡位位于错误校正字段中时的第三二进制编码 。 还可以基于卡住位的值进一步选择新的状态信息，例如，对应于该卡住位的状态位从与该卡位的值匹配的新状态信息中分配一位值。
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公开(公告)号：US10235215B2
公开(公告)日：2019-03-19
申请号：US12024169
申请日：2008-02-01
摘要： A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.
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7.发明申请公开(公告)号：US20130205120A1
公开(公告)日：2013-08-08
申请号：US13369029
申请日：2012-02-08
IPC分类号： G06F9/312
CPC分类号： G06F9/52 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F12/0831
摘要： A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining that the load instruction is resolved based upon receipt of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.
摘要翻译： 一种用于处理指示序列的技术，该指令序列包括屏障指令，屏障指令之前的加载指令，以及跟随障碍指令之后的随后存储器访问指令，包括：基于接收到最早的良好组合响应来确定加载指令是否被解决 用于与加载指令相对应的读取操作和用于加载指令的数据。 该技术还包括如果在完成屏障指令之前没有启动后续存储器访问指令的执行，则响应于确定完成的屏障指令启动后续存储器访问指令的执行。 该技术还包括如果在完成屏障指令之前启动后续存储器访问指令的执行，则响应于确定所完成的屏障指令而中断，跟踪关于无效的后续存储器访问指令。
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8.发明授权Processor, data processing system and method supporting a shared global coherency state 失效处理器，数据处理系统和支持共享全局一致性状态的方法公开(公告)号：US08495308B2
公开(公告)日：2013-07-23
申请号：US11539694
申请日：2006-10-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. According to a method of data processing, a cache line is buffered in a data array of the cache memory and a state field in a cache directory of the cache memory is set to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in said second coherency domain may hold a copy of the cache line.
摘要翻译： 多处理器数据处理系统至少包括第一和第二相干域，其中第一相干域包括系统存储器和高速缓冲存储器。 根据数据处理的方法，将高速缓存行缓冲在高速缓冲存储器的数据阵列中，高速缓冲存储器的高速缓存目录中的状态字段被设置为一致性状态，以指示高速缓存行在数据中是有效的 数组，高速缓存存储器行被非排他地保存在高速缓冲存储器中，并且所述第二相干域中的另一个高速缓冲存储器可以保存高速缓存行的副本。
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公开(公告)号：US08312220B2
公开(公告)日：2012-11-13
申请号：US12420933
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/12
摘要： In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.
摘要翻译： 响应于多个处理单元中的第一处理单元的数据请求，第一处理单元从第一处理单元的较低级高速缓存中选择要丢弃的牺牲高速缓存行，并且确定是否设置了模式。 如果不是，则第一处理单元在互连结构上发出识别受害者高速缓存行的LCO命令，并指示较低级别的高速缓存是预期的目的地。 如果模式被设置，则第一处理单元发出具有替代预定目的地的停顿命令。 响应于指示LCO命令成功的LCO命令的一致性响应，第一处理单元从其较低级高速缓存中去除受害者高速缓存行，并且将受害者高速缓存行保持在数据处理系统的其他地方。 该模式可以设置为抑制系统内存的丢弃，例如进行测试。
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公开(公告)号：US08209489B2
公开(公告)日：2012-06-26
申请号：US12256064
申请日：2008-10-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0897 , Y02D10/13
摘要： A processing unit for a multiprocessor data processing system includes a processor core and a cache hierarchy coupled to the processor core to provide low latency data access. The cache hierarchy includes an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache. In response to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system.
摘要翻译： 用于多处理器数据处理系统的处理单元包括处理器核心和耦合到处理器核心的高速缓存层级以提供低延迟数据访问。 高速缓存层级包括耦合到处理器核心的高级缓存和耦合到高级缓存的较低级别的牺牲缓存。 响应于在高级缓存中丢失的处理器核心的预取请求，较低级别的受害者缓存确定预取请求是否丢失在较低级别的受害者缓存的目录中，并且如果是，则在下级缓存中分配状态机 通过向多处理器数据处理系统的至少一个其他处理单元发出预取请求来服务于预取请求。
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