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93 条记录 (耗时 0.047 秒)

    Transmitter bandwidth optimization circuit
    61.
    发明授权
    Transmitter bandwidth optimization circuit 有权
    发射机带宽优化电路

    公开(公告)号：US08219040B2

    公开(公告)日：2012-07-10

    申请号：US11769128

    申请日：2007-06-27

    申请人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Joseph Natonio ,  James D. Rockrohr ,  Huihao Xu ,  Steven J. Zier

    发明人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Joseph Natonio ,  James D. Rockrohr ,  Huihao Xu ,  Steven J. Zier

    IPC分类号： H04B1/02

    CPC分类号： H04L25/0286 ,  H04L25/0272

    摘要： A method is provided for operating a transmitter integrated in a microelectronic element. In a calibration phase, a plurality of operational parameters are stored for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. Upon detecting an operating condition such as a temperature or power supply voltage level, the corresponding stored operational parameter is applied to the transmitter to control the frequency response.

    摘要翻译： 提供了一种用于操作集成在微电子元件中的发射器的方法。 在校准阶段中，存储多个操作参数，用于在多个对应的操作条件中的每一个下控制发射机的频率响应。 在检测到诸如温度或电源电压电平的操作条件时，将相应的存储的操作参数应用于发射机以控制频率响应。

    Adaptive noise suppression using a noise look-up table
    62.
    发明授权
    Adaptive noise suppression using a noise look-up table 有权
    使用噪声查找表进行自适应噪声抑制

    公开(公告)号：US08077534B2

    公开(公告)日：2011-12-13

    申请号：US12183099

    申请日：2008-07-31

    申请人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Sebastian T. Ventrone

    IPC分类号： G11C7/02

    CPC分类号： G06F1/03 ,  G06F1/26

    摘要： A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.

    摘要翻译： 一种用于集成电路的电源网络的主动噪声抑制系统和方法。 该系统和方法包括：向存储元件接收IC事件序列，将IC事件序列与第二存储器元件中的存储位置相关联，存储位置包括抗噪声响应签名，并将抗噪声响应签名 在执行第一IC事件序列时，在集成电路的至少一部分中，主动地在电力供应网络中产生抗噪声响应。 基于通过集成电路执行IC事件序列进行的噪声测量可以自适应地更新和/或创建抗噪声响应签名。

    Systems and arrangements for clock and data recovery in communications
    64.
    发明授权
    Systems and arrangements for clock and data recovery in communications 有权
    通信中时钟和数据恢复的系统和安排

    公开(公告)号：US07983368B2

    公开(公告)日：2011-07-19

    申请号：US11608948

    申请日：2006-12-11

    申请人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

    发明人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

    IPC分类号： H04L7/00

    CPC分类号： H04L7/042 ,  H04L7/0004 ,  H04L7/0334

    摘要： A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.

    摘要翻译： 公开了一种用于数字数据接收机的采样时钟信号控制器。 可以识别数据波形的特定位模式，并且可以分析对应于特定位模式的波形的存储时间采样以改善采样时钟信号的定时。 可以利用已知位图案上的这些“时间幅度”采样来确定数据波形上的样本是否应在眼图的中心，眼图的中心之前或眼图的中心之后 和什么时间改变。 因此，可以利用单个低功率时钟来调整采样时钟的定时，从而实现改进的通信扫描。 这种单一时钟系统降低了功率需求并提高了精度。

    Test circuit for serial link receiver
    65.
    发明授权
    Test circuit for serial link receiver 有权
    串行链路接收机测试电路

    公开(公告)号：US07940846B2

    公开(公告)日：2011-05-10

    申请号：US11621016

    申请日：2007-01-08

    申请人： Hayden C. Cranford, Jr. ,  Daniel P. Greenberg ,  Joseph M. Stevens ,  Westerfield J. Ficken

    发明人： Hayden C. Cranford, Jr. ,  Daniel P. Greenberg ,  Joseph M. Stevens ,  Westerfield J. Ficken

    IPC分类号： H04B3/00

    CPC分类号： G01R31/31715

    摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

    摘要翻译： 用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。 第一电流源与第二电流源对称地匹配。 第一电流源的第一开关被接通以允许其电荷保持机构被充电。 第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。 电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。 接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

    System and method for balancing delay of signal communication paths through well voltage adjustment
    69.
    发明授权
    System and method for balancing delay of signal communication paths through well voltage adjustment 有权
    通过井电压调整来平衡信号通信路径的延迟的系统和方法

    公开(公告)号：US07404114B2

    公开(公告)日：2008-07-22

    申请号：US10906343

    申请日：2005-02-15

    申请人： Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

    发明人： Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

    IPC分类号： G01R31/28

    CPC分类号： H03K5/133 ,  H03K2005/00032

    摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

    摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

    On-chip electromigration monitoring system
    70.
    发明授权
    On-chip electromigration monitoring system 有权
    片上电迁移监控系统

    公开(公告)号：US07394273B2

    公开(公告)日：2008-07-01

    申请号：US11306985

    申请日：2006-01-18

    申请人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

    发明人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2858 ,  G01R31/2884 ,  G01R31/318533

    摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.

    摘要翻译： 提供一种封装的半导体芯片，其包括半导体芯片和封装元件。 半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。 封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。 半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。 半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时 被监测元件的电阻超过阈值。