公开(公告)号：US20090132985A1

公开(公告)日：2009-05-21

申请号：US11985966

申请日：2007-11-19

申请人： Louis L. Hsu ,  Hayden C. Cranford, JR. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Hayden C. Cranford, JR. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/2858

摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。 该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。 可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。 每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。

公开(公告)号：US07394273B2

公开(公告)日：2008-07-01

申请号：US11306985

申请日：2006-01-18

申请人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

IPC分类号： G01R31/02

CPC分类号： G01R31/2858 ,  G01R31/2884 ,  G01R31/318533

摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.

摘要翻译： 提供一种封装的半导体芯片，其包括半导体芯片和封装元件。 半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。 封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。 半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。 半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时 被监测元件的电阻超过阈值。

公开(公告)号：US07840916B2

公开(公告)日：2010-11-23

申请号：US11985966

申请日：2007-11-19

申请人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/2858

摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。 该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。 可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。 每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。

公开(公告)号：US07719302B2

公开(公告)日：2010-05-18

申请号：US12215732

申请日：2008-06-30

申请人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

IPC分类号： G01R31/02

CPC分类号： G01R31/2858 ,  G01R31/2884 ,  G01R31/318533

摘要： A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.

摘要翻译： 提供了一种用于监测半导体芯片组件内的互连电阻的方法。半导体芯片组件可以包括具有在半导体芯片的表面处露出的触点的半导体芯片和具有与触点导电连通的露出端子的基板。 半导体芯片的多个受监测元件可以包括导电互连，每个导体互连通过半导体芯片内的布线互连半导体芯片的相应的一对节点。 在这种方法的示例中，在半导体芯片组件的寿命期间，跨越每个被监测元件的电压降与在半导体芯片上的相应参考元件上的参考电压降在多个不同时间进行比较。 以这种方式，当这种被监视的元件的电阻超过阈值时，可以检测它。 基于这种比较的结果，可以做出是否指示动作条件的决定。

公开(公告)号：US20080265931A1

公开(公告)日：2008-10-30

申请号：US12215732

申请日：2008-06-30

申请人： Louis L. Hsu ,  Hayden C. Cranford ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Hayden C. Cranford ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  G01R31/2884 ,  G01R31/318533

摘要： A method is provided for monitoring interconnect resistance within a semiconductor chip assembly. A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.

摘要翻译： 提供了一种用于监测半导体芯片组件内的互连电阻的方法。 半导体芯片组件可以包括具有暴露在半导体芯片的表面处的触点的半导体芯片和具有与触点导电连通的暴露端子的基板。 半导体芯片的多个受监测元件可以包括导电互连，每个导体互连通过半导体芯片内的布线互连半导体芯片的相应的一对节点。 在这种方法的示例中，在半导体芯片组件的寿命期间，跨越每个被监测元件的电压降与在半导体芯片上的相应参考元件上的参考电压降在多个不同时间进行比较。 以这种方式，当这种被监视的元件的电阻超过阈值时，可以检测它。 基于这种比较的结果，可以做出是否指示动作条件的决定。

公开(公告)号：US20070164768A1

公开(公告)日：2007-07-19

申请号：US11306985

申请日：2006-01-18

申请人： Louis Hsu ,  Hayden Cranford ,  Oleg Gluschenkov ,  James Mason ,  Michael Sorna ,  Chih-Chao Yang

发明人： Louis Hsu ,  Hayden Cranford ,  Oleg Gluschenkov ,  James Mason ,  Michael Sorna ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  G01R31/2884 ,  G01R31/318533

摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.

摘要翻译： 提供一种封装的半导体芯片，其包括半导体芯片和封装元件。 半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。 封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。 半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。 半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间，将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时 被监测元件的电阻超过阈值。

公开(公告)号：US20120188002A1

公开(公告)日：2012-07-26

申请号：US13438230

申请日：2012-04-03

申请人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

IPC分类号： H03K17/687 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

摘要翻译： 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。 开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。 泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

公开(公告)号：US20110254121A1

公开(公告)日：2011-10-20

申请号：US12761780

申请日：2010-04-16

申请人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： H01L23/525 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

摘要翻译： 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

公开(公告)号：US20110069425A1

公开(公告)日：2011-03-24

申请号：US12565802

申请日：2009-09-24

申请人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

IPC分类号： H01G4/38 ,  H01L21/02 ,  H03K17/687

CPC分类号： H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

摘要翻译： 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。 开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。 泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

公开(公告)号：US07092235B2

公开(公告)日：2006-08-15

申请号：US11043760

申请日：2005-01-26

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01G4/06

CPC分类号： H01G4/255 ,  H01L22/22 ,  H01L28/40

摘要： A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.

摘要翻译： 本文公开了一种用于调节形成在衬底上的片上电容器的电容的方法和装置。 多个导电层被一层电介质材料隔开。 电容器的电介质材料暴露于离子束。 离子束包括至少一种材料的离子，以改变介电材料的介电常数。