公开(公告)号：US5428237A

公开(公告)日：1995-06-27

申请号：US158371

申请日：1993-11-29

申请人： Hiroshi Yuzurihara ,  Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Tetsunobu Kochi

发明人： Hiroshi Yuzurihara ,  Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Tetsunobu Kochi

IPC分类号： G11C17/16 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/112 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7851 ,  G11C17/16 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/8238 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/78612 ,  H01L29/78639 ,  H01L27/112 ,  H01L27/1211 ,  Y10S257/901

摘要： An insulated gate type transistor includes a plurality of major electrode regions, a channel region provided between the plurality of major electrode regions, a gate electrode provided on the channel region with a gate insulating film therebetween, and a semiconductor region provided in contact with the channel region, the semiconductor region having the same conductivity type as that of the channel region and a higher impurity concentration than the channel region. The gate electrode has at least two opposing portions. The plurality of major electrode regions are provided on an substrate insulating film. The transistor is activated in a state where the semiconductor region is maintained at a predetermined voltage. A semiconductor device includes a plurality of memory cells, each of which includes the aforementioned insulated gate type transistor and an electrically breakable memory element provided on one of the major electrode regions.

摘要翻译： 绝缘栅型晶体管包括多个主电极区域，设置在多个主电极区域之间的沟道区域，设置在沟道区域上的栅极电极之间的栅极绝缘膜，以及设置成与沟道接触的半导体区域 区域，具有与沟道区相同的导电类型和比沟道区更高的杂质浓度的半导体区。 栅电极具有至少两个相对的部分。 多个主电极区域设置在基板绝缘膜上。 晶体管在半导体区域保持在预定电压的状态下被激活。 半导体器件包括多个存储单元，每个存储单元包括上述绝缘栅型晶体管和设置在其中一个主电极区上的电可破坏存储元件。