公开(公告)号：US5612230A

公开(公告)日：1997-03-18

申请号：US417901

申请日：1995-04-06

申请人： Hiroshi Yuzurihara ,  Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Tetsunobu Kochi

发明人： Hiroshi Yuzurihara ,  Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Tetsunobu Kochi

IPC分类号： G11C17/16 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/112 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265 ,  H01L21/20

CPC分类号： H01L29/7851 ,  G11C17/16 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/8238 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/78612 ,  H01L29/78639 ,  H01L27/112 ,  H01L27/1211 ,  Y10S257/901

摘要： An insulated gate type transistor includes a plurality of major electrode regions, a channel region provided between the plurality of major electrode regions, a gate electrode provided on the channel region with a gate insulating film therebetween, and a semiconductor region provided in contact with the channel region, the semiconductor region having the same conductivity type as that of the channel region and a higher impurity concentration than the channel region. The gate electrode has at least two opposing portions. The plurality of major electrode regions are provided on an substrate insulating film. The transistor is activated in a state where the semiconductor region is maintained at a predetermined voltage. A semiconductor device includes a plurality of memory cells, each of which includes the aforementioned insulated gate type transistor and an electrically breakable memory element provided on one of the major electrode regions.

摘要翻译： 绝缘栅型晶体管包括多个主电极区域，设置在多个主电极区域之间的沟道区域，设置在沟道区域上的栅极电极之间的栅极绝缘膜，以及设置成与沟道接触的半导体区域 区域，具有与沟道区相同的导电类型和比沟道区更高的杂质浓度的半导体区。 栅电极具有至少两个相对的部分。 多个主电极区域设置在基板绝缘膜上。 晶体管在半导体区域保持在预定电压的状态下被激活。 半导体器件包括多个存储单元，每个存储单元包括上述绝缘栅型晶体管和设置在其中一个主电极区上的电可破坏存储元件。

公开(公告)号：US5428237A

公开(公告)日：1995-06-27

申请号：US158371

申请日：1993-11-29

申请人： Hiroshi Yuzurihara ,  Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Tetsunobu Kochi

发明人： Hiroshi Yuzurihara ,  Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Tetsunobu Kochi

IPC分类号： G11C17/16 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/112 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7851 ,  G11C17/16 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/8238 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/78612 ,  H01L29/78639 ,  H01L27/112 ,  H01L27/1211 ,  Y10S257/901

摘要： An insulated gate type transistor includes a plurality of major electrode regions, a channel region provided between the plurality of major electrode regions, a gate electrode provided on the channel region with a gate insulating film therebetween, and a semiconductor region provided in contact with the channel region, the semiconductor region having the same conductivity type as that of the channel region and a higher impurity concentration than the channel region. The gate electrode has at least two opposing portions. The plurality of major electrode regions are provided on an substrate insulating film. The transistor is activated in a state where the semiconductor region is maintained at a predetermined voltage. A semiconductor device includes a plurality of memory cells, each of which includes the aforementioned insulated gate type transistor and an electrically breakable memory element provided on one of the major electrode regions.

摘要翻译： 绝缘栅型晶体管包括多个主电极区域，设置在多个主电极区域之间的沟道区域，设置在沟道区域上的栅极电极之间的栅极绝缘膜，以及设置成与沟道接触的半导体区域 区域，具有与沟道区相同的导电类型和比沟道区更高的杂质浓度的半导体区。 栅电极具有至少两个相对的部分。 多个主电极区域设置在基板绝缘膜上。 晶体管在半导体区域保持在预定电压的状态下被激活。 半导体器件包括多个存储单元，每个存储单元包括上述绝缘栅型晶体管和设置在其中一个主电极区上的电可破坏存储元件。

公开(公告)号：US5567962A

公开(公告)日：1996-10-22

申请号：US263147

申请日：1994-06-21

申请人： Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Hiroshi Yuzurihara ,  Tetsunobu Kohchi

发明人： Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Hiroshi Yuzurihara ,  Tetsunobu Kohchi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/102 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

CPC分类号： H01L29/7851 ,  H01L21/823475 ,  H01L27/1026 ,  H01L27/10805 ,  H01L27/115 ,  H01L29/66795

摘要： A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.

摘要翻译： 一种半导体存储器件，包括：绝缘栅晶体管，具有沿着基板的主表面设置的多个主电极区域和设置在所述多个主电极区域之间的沟道区域;以及栅极电极，设置在所述沟道区域上， 绝缘体之间，所述栅电极具有至少两个相对的部分; 以及设置在所述主电极区域之一上的电可破坏的存储元件。

公开(公告)号：US5331197A

公开(公告)日：1994-07-19

申请号：US870258

申请日：1992-04-17

申请人： Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Hiroshi Yuzurihara ,  Tetsunobu Kohchi

发明人： Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Hiroshi Yuzurihara ,  Tetsunobu Kohchi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/102 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

CPC分类号： H01L29/7851 ,  H01L21/823475 ,  H01L27/1026 ,  H01L27/10805 ,  H01L27/115 ,  H01L29/66795

摘要： A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.

摘要翻译： 一种半导体存储器件，包括：绝缘栅晶体管，具有沿着基板的主表面设置的多个主电极区域和设置在所述多个主电极区域之间的沟道区域;以及栅极电极，设置在所述沟道区域上， 绝缘体之间，所述栅电极具有至少两个相对的部分; 以及设置在所述主电极区域之一上的电可破坏的存储元件。

公开(公告)号：US5595920A

公开(公告)日：1997-01-21

申请号：US417831

申请日：1995-04-06

申请人： Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Hiroshi Yuzurihara ,  Tetsunobu Kohchi

发明人： Mamoru Miyawaki ,  Akira Ishizaki ,  Genzo Momma ,  Hiroshi Yuzurihara ,  Tetsunobu Kohchi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/102 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/7851 ,  H01L21/823475 ,  H01L27/1026 ,  H01L27/10805 ,  H01L27/115 ,  H01L29/66795

摘要： A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.

摘要翻译： 一种半导体存储器件，包括：绝缘栅晶体管，具有沿着基板的主表面设置的多个主电极区域和设置在所述多个主电极区域之间的沟道区域;以及栅极电极，设置在所述沟道区域上， 绝缘体之间，所述栅电极具有至少两个相对的部分; 以及设置在所述主电极区域之一上的电可破坏的存储元件。

公开(公告)号：US5561317A

公开(公告)日：1996-10-01

申请号：US478447

申请日：1995-06-07

申请人： Genzo Momma ,  Hiroshi Yuzurihara

发明人： Genzo Momma ,  Hiroshi Yuzurihara

IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L23/544

CPC分类号： G03F7/70433 ,  G03F7/2002 ,  G03F7/70475 ,  H01L21/0274 ,  H01L2924/0002

摘要： Disclosed is a method of manufacturing semiconductor devices in which a desired pattern having an area size larger than the field size that can be obtained in one exposure process step of an exposure device is formed. The manufacturing method includes the steps of dividing the desired pattern into a plurality of portions, and conducting exposure on the dividing patterns in a joined fashion.

摘要翻译： 公开了一种制造半导体器件的方法，其中形成了具有比在曝光装置的一个曝光处理步骤中可获得的场尺寸大的面积尺寸的期望图案。 该制造方法包括以下步骤：将期望的图案分成多个部分，并以连接的方式在分割图案上进行曝光。

公开(公告)号：US5192680A

公开(公告)日：1993-03-09

申请号：US360341

申请日：1989-06-02

申请人： Yasuhiro Naruse ,  Genzo Momma ,  Hiroshi Yuzurihara

发明人： Yasuhiro Naruse ,  Genzo Momma ,  Hiroshi Yuzurihara

IPC分类号： H01L21/205 ,  H01L21/027 ,  H01L21/20 ,  H01L21/30

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0262 ,  Y10S438/975

摘要： A method for producing a semiconductor device containing steps of forming a stepped pattern on the surface of a semiconductor substrate and forming a gaseous grown crystal layer thereon, which comprises positioning an alignment pattern (for example 6c) included in the first-mentioned pattern diagonally with respect to an in-plane direction of faster pattern growth in said gaseous crystal growth.

摘要翻译： 一种用于制造半导体器件的方法，包括在半导体衬底的表面上形成阶梯状图案并在其上形成气态生长晶体层的步骤，其包括将包括在第一提到的图案中的对准图案（例如6c）与对角线对准地定位 相对于所述气态晶体生长中更快图案生长的面内方向。

公开(公告)号：US5861233A

公开(公告)日：1999-01-19

申请号：US662200

申请日：1996-06-11

申请人： Yasuhiro Sekine ,  Genzo Momma ,  Hiroshi Yuzurihara

发明人： Yasuhiro Sekine ,  Genzo Momma ,  Hiroshi Yuzurihara

IPC分类号： G03F1/68 ,  G03F1/80 ,  G03F7/004 ,  G03F7/20 ,  H01L21/033 ,  H01L21/263 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/321 ,  G03C5/00 ,  B05D3/06 ,  B44C1/22

CPC分类号： G03F7/2065 ,  G03F7/004 ,  G03F7/2043 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/263 ,  H01L21/3086 ,  H01L21/321

摘要： A pattern forming method comprises subjecting a surface of a semiconductor substrate to a surface treatment for imparting hydrogen atoms, irradiating a desired region of said surface with an energy ray, selectively forming a metal film on a non-irradiated region other than the desired region, and etching said semiconductor substrate using said metal film as a mask.

摘要翻译： 图案形成方法包括使半导体衬底的表面进行表面处理以赋予氢原子，用能量射线照射所述表面的所需区域，在除所需区域之外的非照射区域上选择性地形成金属膜， 并使用所述金属膜作为掩模蚀刻所述半导体衬底。

公开(公告)号：US5731131A

公开(公告)日：1998-03-24

申请号：US395183

申请日：1995-02-27

申请人： Genzo Momma ,  Hiroshi Yuzurihara

发明人： Genzo Momma ,  Hiroshi Yuzurihara

IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L21/30 ,  G03F9/00

CPC分类号： G03F7/70433 ,  G03F7/2002 ,  G03F7/70475 ,  H01L21/0274

摘要： Disclosed is a method of manufacturing semiconductor devices in which a desired pattern having an area size larger than the field size that can be obtained in one exposure process step of an exposure device is formed. The manufacturing method includes the steps of dividing the desired pattern into a plurality of portions, and conducting exposure on the dividing patterns in a joined fashion.

公开(公告)号：US20120200751A1

公开(公告)日：2012-08-09

申请号：US13365146

申请日：2012-02-02

申请人： Taro Kato ,  Mineo Shimotsusa ,  Hiroaki Sano ,  Takeshi Ichikawa ,  Yasuhiro Sekine ,  Mahito Shinohara ,  Genzo Momma

发明人： Taro Kato ,  Mineo Shimotsusa ,  Hiroaki Sano ,  Takeshi Ichikawa ,  Yasuhiro Sekine ,  Mahito Shinohara ,  Genzo Momma

IPC分类号： H04N5/335

CPC分类号： H01L27/14627 ,  H01L27/14621 ,  H01L27/14629 ,  H01L27/1463

摘要： A photoelectric conversion apparatus includes a semiconductor substrate having a photoelectric conversion portion. An insulator is provided on the semiconductor substrate. The insulator has a hole corresponding to the photoelectric conversion portion. A waveguide member is provided in the hole. An in-layer lens is provided on a side of the waveguide member farther from the semiconductor substrate. A first intermediate member is provided between the waveguide member and the in-layer lens. The first intermediate member has a lower refractive index than the in-layer lens.

摘要翻译： 光电转换装置包括具有光电转换部分的半导体衬底。 绝缘体设置在半导体衬底上。 绝缘体具有与光电转换部对应的孔。 波导构件设置在孔中。 在距离半导体衬底更远的波导构件的一侧设置有层内透镜。 第一中间构件设置在波导构件和内层透镜之间。 第一中间构件具有比层内透镜低的折射率。