公开(公告)号：US12111392B2

公开(公告)日：2024-10-08

申请号：US17448609

申请日：2021-09-23

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Farhan Bin Khalid ,  Mayeul Jeannin ,  Markus Bichl

IPC: G01S13/89 ,  G01S13/58 ,  G01S13/931

CPC classification number: G01S13/89 ,  G01S13/584 ,  G01S13/931

Abstract: The present disclosure relates to a concept for detecting radar targets. A plurality of first receive signals is received from first antennas of an antenna array. A first combined range-Doppler map is determined by combining range-Doppler maps of each of the first antennas. First confirmable range-Doppler cells of the first combined range-Doppler map are determined which match a predetermined confirmation criterion. A plurality of second receive signals is received from second antennas of the antenna array. A second combined range-Doppler map is determined by combining range-Doppler maps of each of the second antennas. Second confirmable range-Doppler cells of the second combined range-Doppler map are determined which match the predetermined confirmation criterion. The first and second confirmable range-Doppler cells are combined to obtain a set of confirmable range-Doppler cells. Values of the first and the second combined range-Doppler maps corresponding to the set of confirmable range-Doppler cells are summed to obtain summed values of the combined confirmable range-Doppler cells. Summed values of the total confirmable range-Doppler cells exceeding a predefined selection threshold are selected for target detection.

公开(公告)号：US12013484B2

公开(公告)日：2024-06-18

申请号：US17324375

申请日：2021-05-19

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Dian Tresna Nugraha ,  Simon Achatz

IPC: G01S7/40 ,  G01S7/35 ,  G01S13/34 ,  G01S13/87 ,  G01S13/931

CPC classification number: G01S7/4021 ,  G01S7/356 ,  G01S13/87 ,  G01S13/931 ,  G01S13/343

Abstract: According to one embodiment, a radar receiving system is provided comprising a first receiving circuit, a second receiving circuit, a spectral analyzer, an object detector, and a phase compensation circuit. The spectral analyzer is configured to generate, from a first plurality of reception signals, a first set of Fourier transformation output values and, from a second plurality of reception signals, a second set of Fourier transformation output values. The object detector is configured to determine a range/Doppler bin of a plurality of range/Doppler bins as an estimate of a range and speed of an object. The phase compensation circuit is configured to determine a phase offset between the Fourier transformation output values of the first set and second set of Fourier transformation output values and to compensate the phases of at least a part of the second set of Fourier transformation output values by the determined phase offset.

公开(公告)号：US11683049B2

公开(公告)日：2023-06-20

申请号：US16793149

申请日：2020-02-18

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Markus Bichl ,  Romain Ygnace

IPC: H03M7/30 ,  G01S7/35 ,  G01S7/295

CPC classification number: H03M7/6005 ,  G01S7/295 ,  G01S7/352 ,  G01S7/356

Abstract: A processor having a hardware decompressor configured to pad a non-equidistant data set, which is data received at irregular time intervals, with one or more of a predefined value, wherein the data is radar or optical sensor data; and a Fourier transform engine configured to receive the padded non-equidistant data set directly and continuously per data set from the hardware decompressor, and to FFT process the received padded non-equidistant data set.

公开(公告)号：US11513213B2

公开(公告)日：2022-11-29

申请号：US16351169

申请日：2019-03-12

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Farhan Bin Khalid ,  Romain Ygnace

IPC: G01S13/93 ,  G01S7/35 ,  G01S13/931 ,  G01S13/58 ,  G01S7/03 ,  G01S13/524 ,  G01S7/02

Abstract: A method for processing a radar signal is provided. The method may include receiving chirps of a radar signal, sampling the radar signal, dividing the samples that correspond to the chirp of the radar signal into at least two virtual chirps, and processing the radar signal based on the at least two virtual chirps. Also, a corresponding device is provided.

公开(公告)号：US20210364599A1

公开(公告)日：2021-11-25

申请号：US17324375

申请日：2021-05-19

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Dian Tresna Nugraha ,  Simon Achatz

IPC: G01S7/40 ,  G01S13/931 ,  G01S13/87 ,  G01S7/35 ,  G01S13/34

Abstract: According to one embodiment, a radar receiving system is provided comprising a first receiving circuit, a second receiving circuit, a spectral analyzer, an object detector, and a phase compensation circuit. The spectral analyzer is configured to generate, from a first plurality of reception signals, a first set of Fourier transformation output values and, from a second plurality of reception signals, a second set of Fourier transformation output values. The object detector is configured to determine a range/Doppler bin of a plurality of range/Doppler bins as an estimate of a range and speed of an object. The phase compensation circuit is configured to determine a phase offset between the Fourier transformation output values of the first set and second set of Fourier transformation output values and to compensate the phases of at least a part of the second set of Fourier transformation output values by the determined phase offset.

公开(公告)号：US20210364596A1

公开(公告)日：2021-11-25

申请号：US17324675

申请日：2021-05-19

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Simon Achatz ,  Dian Tresna Nugraha ,  Ljudmil Anastasov ,  Markus Bichl ,  Mayeul Jeannin ,  Maximilian Eschbaumer

IPC: G01S7/35 ,  G01S13/536 ,  G01S13/58

Abstract: It is suggested to process radar signals including: (i) receiving reception signals via at least one antenna of a first receiving circuit; (ii) determining an interim result by processing the reception signals via a frequency transformation; (iii) determining an error compensation vector based on the interim result and an expected characteristic; and (iv) applying the error compensation vector on other reception signals that have been processed via the frequency transformation.

公开(公告)号：US20210263706A1

公开(公告)日：2021-08-26

申请号：US17179886

申请日：2021-02-19

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Markus Bichl ,  Dian Tresna Nugraha ,  Romain Ygnace

IPC: G06F7/483 ,  G01S7/288 ,  G01S7/41 ,  G06F7/48

Abstract: A radar device is configured to: select a set of operands comprising several operands, determine a common exponent for the operands of the set of operands, normalize the operands based on the common exponent, compress each operand by reducing the resolution of its mantissa, and store the common exponent and the compressed operands in a memory. Also, a vehicle including such radar device and an according method as well as computer program product are provided.

公开(公告)号：US11099256B2

公开(公告)日：2021-08-24

申请号：US16000979

申请日：2018-06-06

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Christian Schmid ,  Romain Ygnace

IPC: G01S7/295 ,  G01S7/03 ,  G01S7/28 ,  G06F13/30

Abstract: A device for processing radar signals is suggested, the device comprising: (i) a memory, which is arranged to store radar data and (ii) an accessor comprising a DMA engine, wherein the accessor is arranged to access data of the memory via the DMA engine, to filter the accessed data, and to forward the filtered data.

公开(公告)号：US11085994B2

公开(公告)日：2021-08-10

申请号：US16159957

申请日：2018-10-15

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Romain Ygnace

IPC: G01S7/292 ,  G01S7/03 ,  G01S7/288 ,  G01S13/931

Abstract: A radar device including at least three subcircuits, wherein each subcircuit has a cascade input port and a cascade output port and is chained such that the cascade output port of a first subcircuit is connected to the cascade input port of a subsequent subcircuit, the cascade input port of the last subcircuit of the chain is connected to the cascade output port of its preceding subcircuit, and the cascade output port of the last subcircuit of the chain is connectable to an external device, and wherein the at least three subcircuits are configured to conduct a radar computation in a distributed manner such that intermediate results are conveyed towards the last subcircuit of the chain which is configured to combine these results and supply them towards its cascade output port.

公开(公告)号：US20190146058A1

公开(公告)日：2019-05-16

申请号：US16169159

申请日：2018-10-24

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Markus Bichl ,  Romain Ygnace

IPC: G01S7/288 ,  G01S13/26

Abstract: A radar device is disclosed including an input DMA module, at least one processing module, and an output DMA module. The input DMA module is arranged to access a memory and supply data from the memory to the at least one processing module, wherein each of the processing modules is arranged to be enabled or disabled. The at least one processing module that is enabled is arranged to process at least a portion of the data supplied by the input DMA module, and the output DMA module is arranged to store the data that are processed by the at least one processing module that is enabled in the memory. Also, a method for processing data by a radar device is provided.