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公开(公告)号：US20090313484A1
公开(公告)日：2009-12-17
申请号：US12140976
申请日：2008-06-17
IPC分类号： G06F1/28
CPC分类号： G06F1/30 , G06F1/3203
摘要： A method of operating a media player is provided. In one embodiment the method includes receiving a plurality of initially configured video settings for viewing a video segment on the media player for a desired playback duration. The method further includes determining power required to play the video segment based on the initial video settings and playing the video segment if the required power matches or is less than total power available to the media player. In another embodiment, the method may further include, if the required power exceeds the total power available to the media player, adjusting one or more of the initial video settings, either automatically or by user inputs, to reduce the power required to play the requested video segment for the desired playback duration.
摘要翻译： 提供操作媒体播放器的方法。 在一个实施例中，该方法包括接收多个初始配置的视频设置，用于在媒体播放器上观看期望的播放持续时间的视频段。 该方法还包括：如果所需功率匹配或小于媒体播放器可用的总功率，则基于初始视频设置确定播放视频片段所需的功率并播放视频片段。 在另一个实施例中，如果所需功率超过媒体播放器可用的总功率，该方法可以进一步包括：自动地或通过用户输入来调整一个或多个初始视频设置，以减少播放所请求的功率所需的功率 视频段用于所需播放持续时间。
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62.发明授权公开(公告)号：US07430676B2
公开(公告)日：2008-09-30
申请号：US11367813
申请日：2006-03-03
申请人： Paul A. Baker , William C. Athas
发明人： Paul A. Baker , William C. Athas
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
摘要： One embodiment of the present invention provides a system that facilitates changing a clock frequency in a memory system. During operation, the system receives a command to change the clock frequency to a new clock frequency. The system then iteratively changes the clock frequency to the new clock frequency. More specifically, the system starts an iteration by slewing the clock frequency toward the new clock frequency by an increment to reach an intermediate frequency without interfering with normal memory-system operation. Next, the system signals a memory controller to pause normal memory system operation by completing or cancelling all in-flight or outstanding memory system operations and not accepting additional memory operation requests. Upon receiving an acknowledgement from the memory controller that all in-flight or outstanding memory operations have completed or terminated, the system signals the memory controller to cause a delay-locked loop (DLL) inside the memory system to relock to the intermediate frequency. When the DLL relocks to the intermediate frequency, the system completes the iteration by resuming normal memory system operation.
摘要翻译： 本发明的一个实施例提供一种便于改变存储器系统中的时钟频率的系统。 在运行期间，系统接收到将时钟频率更改为新时钟频率的命令。 然后系统将时钟频率迭代地更改为新的时钟频率。 更具体地说，系统通过将时钟频率向新时钟频率转动一个增量来开始迭代，以达到中间频率而不干扰正常的存储系统操作。 接下来，系统通过完成或取消所有的飞行中或未完成的存储器系统操作并且不接受附加的存储器操作请求来通知存储器控制器来暂停正常的存储器系统操作。 在从存储器控制器接收到所有飞行中或未完成的存储器操作已经完成或终止的确认之后，系统发信号通知存储器控制器以使存储器系统内部的延迟锁定环（DLL）重新锁定到中间频率。 当DLL重新锁定到中间频率时，系统通过恢复正常的存储器系统操作来完成迭代。
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公开(公告)号：US20080040055A1
公开(公告)日：2008-02-14
申请号：US11502934
申请日：2006-08-11
摘要： Methods and apparatuses to perform calibration of imprecise sensors for power monitoring in a data-processing system are described. The system includes a load coupled to one or more sensors. An electronic load changes a first input signal through one or more sensors by a predetermined amount. A difference in an output signal from the one or more sensors in response to the changing is obtained. The output signal is measured and sampled. A distribution of samples of the output signal is determined. The estimated parameters of the distribution that most likely to explain actual data are determined. Next, a transfer function of the one or more sensors is determined based on the estimated parameters. The input signal through the load is accurately predicted using the transfer function of the one or more sensors to monitor the power usage by the load.
摘要翻译： 描述了在数据处理系统中执行用于功率监控的不精确传感器的校准的方法和装置。 该系统包括耦合到一个或多个传感器的负载。 电子负载通过一个或多个传感器将第一输入信号改变预定量。 获得响应于变化的来自一个或多个传感器的输出信号的差异。 测量和采样输出信号。 确定输出信号的样本分布。 确定最可能解释实际数据的分布的估计参数。 接下来，基于估计的参数来确定一个或多个传感器的传递函数。 通过一个或多个传感器的传递函数可精确地预测通过负载的输入信号，以监测负载的功率使用情况。
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公开(公告)号：US07202712B2
公开(公告)日：2007-04-10
申请号：US11420950
申请日：2006-05-30
申请人： William C. Athas
发明人： William C. Athas
IPC分类号： H03B28/00
CPC分类号： H03B27/00 , H03B5/1215 , H03B5/1228 , H03K3/03 , H03K3/354
摘要： A multiphase resonant pulse generator (74) has N groups of N−1 switches (44,46,48) which, when activated, form N paths from a power supply (Vdc) to ground or a reference voltage. Here N is a positive integer greater than 2. Each of the paths includes an inductance (38,40,42) and N−1 switches. The signal outputs (X1,X2,X3) from each of the N paths are cross coupled to switches belonging to the other N−1 paths to active or deactivate the groups of switches.
摘要翻译： 多相谐振脉冲发生器（74）具有N组N-1个开关（44,46,48），其在被激活时形成从电源（Vdc）到接地或参考电压的N个路径。 这里N是大于2的正整数。每个路径包括电感（38,40,42）和N-1开关。 来自N个路径中的每一个的信号输出（X 1，X 2，X 3）与属于其它N-1路径的交换机交叉耦合，以激活或去激活该组开关。
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公开(公告)号：US07176712B2
公开(公告)日：2007-02-13
申请号：US11196892
申请日：2005-08-04
申请人： Lars G. Svensson , William C. Athas
发明人： Lars G. Svensson , William C. Athas
IPC分类号： H03K19/003
CPC分类号： H04L25/028 , H03K3/00 , H03K17/00 , H03K19/0005 , H03K19/0019 , H04L25/0278 , H04L25/0286 , H04L25/0298
摘要： A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately-preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.
摘要翻译： 一种用于减少传输线中的反射并且在该过程期间从传输中的负载中恢复能量的系统和方法。 至少使用三个驱动信号电平。 在上升过渡期间，从第二级到第三级的转变以及在下降的转换期间从第二级到第一级的转变被定时与来自紧接在前的转换的反射信号的到达相一致。 有利地，电容器用作中间驱动信号电平的源，并且有利地有助于能量回收和保存。
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66.发明授权Power-efficient, pulsed driving of capacitive loads to controllable voltage levels 有权功率高效的脉冲驱动电容负载到可控电压水平公开(公告)号：US06985142B1
公开(公告)日：2006-01-10
申请号：US09389841
申请日：1999-09-03
申请人： Lars G. Svensson , William C. Athas , Rajat K. Lal
发明人： Lars G. Svensson , William C. Athas , Rajat K. Lal
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G2330/023 , Y10T307/74
摘要： Power-efficient, pulsed driving of capacitive loads to controllable voltage levels, with particular applicability to LCDs. Energy stored in a portion of the capacitive load is recovered during a recovery phase. Time-varying signals are used to drive the load and to recover the stored energy, thus minimizing power losses, using processes named adiabatic charging and adiabatic discharging.
摘要翻译： 功率高效的脉冲驱动电容负载到可控的电压水平，特别适用于LCD。 存储在电容性负载的一部分中的能量在恢复阶段被恢复。 使用时变信号来驱动负载并恢复存储的能量，从而最小化功率损耗，使用称为绝热充电和绝热放电的工艺。
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67.发明授权公开(公告)号：US06889235B2
公开(公告)日：2005-05-03
申请号：US09991098
申请日：2001-11-16
申请人： William C. Athas
发明人： William C. Athas
摘要： One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by converting the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits. Next, the system converts the thermometer code into a one-hot code in which only one bit has a logical one value. Finally, the system converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.
摘要翻译： 本发明的一个实施例提供一种用于量化从n位数字串内的固定位置开始的相同连续数字的数量的系统。 该系统通过将n位字符串转换成温度计代码进行操作，其中温度计代码使用m位来表示n个数字串中的相同连续数字的m个字符串。 接下来，系统将温度计代码转换为仅一位具有逻辑1值的单热代码。 最后，系统将单热代码转换为表示相同连续数位数的对数代码。
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公开(公告)号：US06844833B2
公开(公告)日：2005-01-18
申请号：US10691344
申请日：2003-10-21
CPC分类号： G06F13/4027 , H03M13/23 , H03M13/41
摘要： Methods and apparatus for spreading and concentrating information to constant-weight encode of data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.
摘要翻译： 用于扩展和集中信息以在并行数据线总线上对数据字进行恒权重编码的同时允许跨子字路径进行信息通信的方法和装置。 在一个实施例中，仅通过差分架构获得的数据传输速率仅通过单端架构上的行数小幅增加来实现。 例如，18位数据字需要22个用于传输的编码数据线，其中先前需要16行和32行来传输具有单端和差分架构的未编码数据。 恒定并行编码在并行编码数据线和信号线的高电平和低电位驱动电路中保持恒定电流。
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69.再颁专利System and method for power-efficient charging and discharging of a capacitive load from a single source 失效从单个电源对电容性负载进行高效充电和放电的系统和方法公开(公告)号：USRE37552E1
公开(公告)日：2002-02-19
申请号：US08986327
申请日：1997-12-05
IPC分类号： H02M307
摘要： A system and method for efficiently charging and discharging a capacitive load from a single voltage source. The system includes a first switch for selectively connecting the voltage source to the load and a second switch for selectively providing a short across the load as may be common in the art. A particularly novel aspect of the invention resides in the provision of plural capacitive elements and a switching mechanism for selectively connecting each of the capacitive elements to the load whereby the load is gradually charged or discharged. In the illustrative embodiment, the switching mechanism includes a set of switches for selectively connecting each of the capacitive elements to the capacitive load and a switch control mechanism for selectively activating the switches.
摘要翻译： 一种用于从单个电压源高效地对容性负载进行充电和放电的系统和方法。 该系统包括用于选择性地将电压源连接到负载的第一开关和用于选择性地跨越负载提供短路的第二开关，如本领域常见的那样。 本发明的特别新颖的方面在于提供多个电容元件和用于选择性地将每个电容元件连接到负载的开关机构，由此负载逐渐充电或放电。 在说明性实施例中，切换机构包括用于选择性地将每个电容元件连接到电容性负载的开关组以及用于选择性地启动开关的开关控制机构。
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70.发明授权Apparatus for intrasystem communications within a binary n-cube including buffer lock bit 失效用于在包括缓冲锁定位的二进制n-cube内进行系统间通信的装置
公开(公告)号：US5047917A
公开(公告)日：1991-09-10
申请号：US303977
申请日：1989-01-31
IPC分类号： G06F15/173
CPC分类号： G06F15/17343
摘要： An improved communication system for the prevention of lockup in a computer system of the binary n-cube type. Input circuitry at each of the nodes is connected for receiving messages and includes an input buffer for initially receiving the messages. Output circuitry at each of the nodes is connected for transmitting holding the messages prior to and during transmission thereof. A kernel program at each of the nodes acts as an interface between the user process programs and exclusively controls the receiving and transmitting of messages into and out of the node. There is provision for the user process programs to pass control to the kernel program to request the sending and receiving of messages by the kernel program. A lock bit is associated with each message, sensible by the user process programs, and reset by the kernel program when the kernel program has transferred the associated message. Asynchronous transfer circuitry independently and asynchronously transfers the messages as packets between the buffers of the nodes. There is logic for various decisional matters regarding message sending and receipt. There is blockout prevention logic for refusing to receive a message unless a user process program in the node has reserved a buffer of sufficient size to receive the message and for listing messages waiting to be received for which space has not yet been reserved.
摘要翻译： 一种改进的通信系统，用于防止二进制n型立方体类型的计算机系统中的锁定。 每个节点处的输入电路被连接用于接收消息，并且包括用于初始接收消息的输入缓冲器。 在每个节点处的输出电路被连接用于发送之前和期间的发送。 每个节点上的内核程序用作用户进程程序之间的接口，并专门控制消息的接收和发送进出节点。 用户进程程序提供了向内核程序传递控制权以请求内核程序发送和接收消息的规定。 锁定位与每个消息相关联，由用户进程程序显示，并且当内核程序传送关联的消息时由内核程序重置锁定位。 异步传输电路独立且异步地将消息作为数据包传输到节点的缓冲区之间。 有关消息发送和接收的各种决定事项的逻辑。 除非节点中的用户处理程序已经预留了足够大小的缓冲区以接收消息并列出等待接收的空间尚未被保留的消息，否则存在用于拒绝接收消息的防止阻止逻辑。
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