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    Multiple logical interfaces to a shared coprocessor resource
    63.
    发明授权
    Multiple logical interfaces to a shared coprocessor resource 失效
    到共享协处理器资源的多个逻辑接口

    公开(公告)号：US06829697B1

    公开(公告)日：2004-12-07

    申请号：US09656582

    申请日：2000-09-06

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    IPC分类号： G06F1500

    CPC分类号： G06F15/7864

    摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.

    摘要翻译： 嵌入式处理器复合体包含多个协议处理器单元（PPU）。 每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。 每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。 操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。 指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。

    Instruction memory system for multi-processor environment and disjoint tasks
    64.
    发明授权
    Instruction memory system for multi-processor environment and disjoint tasks 有权
    指令存储系统，用于多处理器环境和不相交任务

    公开(公告)号：US06760743B1

    公开(公告)日：2004-07-06

    申请号：US09477757

    申请日：2000-01-04

    申请人： Marco C. Heddes ,  Mark Anthony Rinaldi ,  Brian Alan Youngman

    发明人： Marco C. Heddes ,  Mark Anthony Rinaldi ,  Brian Alan Youngman

    IPC分类号： G06F900

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space is divided into code segments according to the disjoint tasks to be performed. The instruction codes of each processor are consolidated into one copy for control instructions and duplicate copies for other disjoint tasks such as inbound requests and outbound requests that have greater processor contention. Interleaving of the memory arrays for certain disjoint tasks serves to provide a larger number of instructions for these tasks. The system utilizes arbiters to receive all disjoint tasks and to control multiplexors that send addresses to memory arrays.

    摘要翻译： 指令存储器系统由多个处理器共享，并且系统利用增加的带宽来支持组合的处理器数量。 总指令地址空间根据要执行的不相交任务分为代码段。 每个处理器的指令代码被合并到一个副本中，用于控制指令和其他不相交任务的重复副本，例如具有更大处理器争用的入站请求和出站请求。 用于某些不相交任务的存储器阵列的交织用于为这些任务提供更多数量的指令。 该系统利用仲裁器接收所有不相交的任务，并控制向存储器阵列发送地址的多路复用器。

    Assembler tool for processor-coprocessor computer systems
    65.
    发明授权
    Assembler tool for processor-coprocessor computer systems 失效
    处理器 - 协处理器计算机系统的汇编工具

    公开(公告)号：US06588008B1

    公开(公告)日：2003-07-01

    申请号：US09546755

    申请日：2000-04-11

    申请人： Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    发明人： Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    IPC分类号： G06F945

    CPC分类号： G06F9/30043 ,  G06F8/47 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3885

    摘要： A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.

    摘要翻译： 一种中央处理器 - 协处理器组件，其包括用于将基本中央处理器任务扩展到至少一个协处理器的汇编器软件工具。 重要的是，当对协处理器元素进行更改时，汇编程序软件工具不需要重新构建。 本发明允许基本核心语言处理（CLP）编程模型的组装时间扩展，而不需要重建汇编器工具本身。 汇编器工具包括使得中央处理器能够操纵协处理器寄存器的一组命令，以及协处理器执行指令，其在协处理器上启动命令处理。 本发明通过使得硬件设计者能够更新其协处理器定义文件以反映新的或修改的协处理器，通过多个硬件修订来简化了汇编工具的维护。

    System and computer program for compressing multi-field classification rules
    66.
    发明授权
    System and computer program for compressing multi-field classification rules 有权
    用于压缩多场分类规则的系统和计算机程序

    公开(公告)号：US07752155B2

    公开(公告)日：2010-07-06

    申请号：US12182118

    申请日：2008-07-29

    申请人： Everett A. Corl, Jr. ,  Gordon T. Davis ,  Marco C. Heddes ,  Piyush C. Patel ,  Ravinder K. Sabhikhi

    发明人： Everett A. Corl, Jr. ,  Gordon T. Davis ,  Marco C. Heddes ,  Piyush C. Patel ,  Ravinder K. Sabhikhi

    IPC分类号： G06F17/00 ,  G06N5/02

    CPC分类号： G06N99/005

    摘要： The present invention relates to a system and computer-readable medium for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields. The method of the present invention includes providing a virtual rule table, where the table stores a plurality of field definitions, and for each of the plurality of multi-field classification rules, compressing the rule specification by replacing at least one field definition with an associated index into the virtual rule table. The method also includes storing each of the compressed rule specifications and the virtual rule table in a shared segment of memory.

    摘要翻译： 本发明涉及一种用于在计算机系统中存储多个多场分类规则的系统和计算机可读介质。 每个多字段分类规则包括本身包括多个字段的规则规范和对应于字段的多个字段定义。 本发明的方法包括提供虚拟规则表，其中表存储多个字段定义，并且对于多个多字段分类规则中的每一个，通过用相关联的替换来替换至少一个字段定义来压缩规则规范 索引到虚拟规则表。 该方法还包括将每个压缩规则规范和虚拟规则表存储在存储器的共享段中。

    Efficient timer management system
    67.
    发明授权
    Efficient timer management system 失效
    高效的定时管理系统

    公开(公告)号：US06826761B1

    公开(公告)日：2004-11-30

    申请号：US09675545

    申请日：2000-09-28

    申请人： Philippe Damon ,  Marco C. Heddes

    发明人： Philippe Damon ,  Marco C. Heddes

    IPC分类号： G06F300

    CPC分类号： G06F1/14

    摘要： A timer management system and method for managing timers in both a synchronous and asynchronous system. In one embodiment of the present invention, a timer management system comprises an application program interface (API) for providing a set of synchronous functions allowing an application to functionally operate on the timer. The timer management system further comprises a timer database for storing timer-related information. Furthermore, the timer management system comprises a timer services for detecting the expiring of the timer. A handle function of the timer services allows an asynchronous application, i.e., application in a multi-task system, to synchronously act on the timer. That is, when a timer in a asynchronous system times-out, the handle function allows the asynchronous application to act on the expired timer without incurring an illegal time-out message. In another embodiment of the present invention, a timer may be reinitialized from the same allocated block of memory used to create the timer. In another embodiment of the present invention, a time-out message may be sent using the same allocated block of memory used to create the timer.

    摘要翻译： 一种用于管理同步和异步系统中定时器的定时器管理系统和方法。 在本发明的一个实施例中，定时器管理系统包括用于提供一组同步功能的应用程序接口（API），允许应用在定时器上进行功能操作。 定时器管理系统还包括用于存储定时器相关信息的定时器数据库。 此外，定时器管理系统包括用于检测定时器到期的定时器服务。 定时器服务的句柄功能允许异步应用，即多任务系统中的应用程序同步地对定时器作用。 也就是说，当异步系统中的定时器超时时，句柄功能允许异步应用程序对过期的定时器进行操作，而不会引起非法超时消息。 在本发明的另一个实施例中，定时器可以从用于创建定时器的相同的分配的存储块重新初始化。 在本发明的另一个实施例中，可以使用用于创建定时器的相同的分配的存储块来发送超时消息。

    System and method for delayed increment of a counter
    69.
    发明授权
    System and method for delayed increment of a counter 失效
    计数器延迟增量的系统和方法

    公开(公告)号：US06996737B2

    公开(公告)日：2006-02-07

    申请号：US10680521

    申请日：2003-10-07

    申请人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    发明人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    IPC分类号： G06F1/04

    CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

    摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.

    摘要翻译： 提供了用于执行延迟计数器增量的方法和结构。 该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。 在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。 因此，计数器递增指令被改变。 延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。 在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。 这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。

    Method for defining and controlling the overall behavior of a network processor device
    70.
    发明授权
    Method for defining and controlling the overall behavior of a network processor device 有权
    用于定义和控制网络处理器设备的整体行为的方法

    公开(公告)号：US06763375B1

    公开(公告)日：2004-07-13

    申请号：US09547362

    申请日：2000-04-11

    申请人： Claude Basso ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Seeta Hariharan ,  Sridhar Rao ,  Sonia Kiang Rovner

    发明人： Claude Basso ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Seeta Hariharan ,  Sridhar Rao ,  Sonia Kiang Rovner

    IPC分类号： G06F1300

    CPC分类号： H04L41/0803 ,  H04L29/06 ,  H04L69/18

    摘要： A system and method for controlling overall behavior of a network processor device implemented in a network processing environment servicing a communications network. The method includes steps of receiving a guided control frame including one or more control functions for configuring various functional devices within the network processor with device control parameter data; a step of forwarding one or more control functions from a received control frame to a functional device within the network processor to be configured; and, executing the control functions as specified in the control frame. A novel control frame data structure and communications infrastructure is implemented whereby any network processor device operating in a distributed network processing environment may be controlled in accordance with executed control functions and device control parameter data.

    摘要翻译： 一种用于控制在为通信网络服务的网络处理环境中实现的网络处理器设备的整体行为的系统和方法。 该方法包括以下步骤：接收包括用于使用设备控制参数数据配置网络处理器内的各种功能设备的一个或多个控制功能的引导控制帧; 将一个或多个控制功能从接收到的控制帧转发到要配置的网络处理器内的功能设备的步骤; 并且执行控制帧中指定的控制功能。 实现新颖的控制帧数据结构和通信基础设施，从而可以根据执行的控制功能和设备控制参数数据来控制在分布式网络处理环境中操作的任何网络处理器设备。