公开(公告)号：US08451158B2

公开(公告)日：2013-05-28

申请号：US13174273

申请日：2011-06-30

申请人： Yu Liao ,  Hongwei Song

发明人： Yu Liao ,  Hongwei Song

IPC分类号： H03M1/12

CPC分类号： H03M1/0602 ,  H03M1/1215

摘要： Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output.

摘要翻译： 本发明的各种实施例提供了用于执行模数转换的系统，装置和方法。 例如，讨论了包括模拟输入，多个模数转换器和广义波束形成器的模数转换器电路。 模数转换器可操作以接收模拟输入并产生多个数字流。 每个模数转换器对具有不同相位偏移的模拟输入进行采样。 广义波束形成器可操作以加权并组合数字流以产生数字输出。

公开(公告)号：US08352841B2

公开(公告)日：2013-01-08

申请号：US12491038

申请日：2009-06-24

申请人： Lingyan Sun ,  Hongwei Song ,  Yuan Xing Lee

发明人： Lingyan Sun ,  Hongwei Song ,  Yuan Xing Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/45 ,  H03M13/1145 ,  H03M13/3905 ,  H03M13/4146

摘要： Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations.

摘要翻译： 本发明的各种实施例提供了用于故障存储器管理的系统和方法。 例如，公开了一种用于乱序数据处理的方法。 该方法包括提供一个乱序码字存储器电路，其包括码字存储器区域中的多个码字存储器位置和索引区域中相同数量的索引值。 每个索引值对应于码字存储器位置中的相应一个。 所述方法还包括接收数据集; 将所述数据集存储到所述码字存储器位置之一; 接收存储在码字存储器位置之一中的数据集已经完成处理的指示; 以及将与所述码字存储器位置之一相对应的索引值与对应于未使用的码字存储器位置的一个或多个其他索引值进行分组。

公开(公告)号：US08341495B2

公开(公告)日：2012-12-25

申请号：US13469746

申请日：2012-05-11

申请人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

发明人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

IPC分类号： H03M13/00 ,  H03M13/03

CPC分类号： H03M13/1128 ,  H03M13/17

摘要： The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal via the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

摘要翻译： 本发明是用于检测短脉冲串错误的装置。 该设备包括第一信号输入，其中第一信号输入被配置为接收第一信号。 该设备包括第二信号输入，其中第二信号输入被配置为接收第二信号。 该器件包括逻辑门，其中逻辑门可操作用于经由第一信号输入接收第一信号，经由第二信号输入接收第二信号，并且基于接收到的第一信号和第二信号产生逻辑输出门信号 信号。 此外，该器件包括滤波器，其中滤波器被配置为从逻辑门接收逻辑输出门信号，并且基于接收的逻辑输出门信号产生滤波器输出信号，其中滤波器输出信号可用于标记误差。

公开(公告)号：US20120158810A1

公开(公告)日：2012-06-21

申请号：US12972942

申请日：2010-12-20

申请人： Yu Liao ,  Hongwei Song ,  Lingyan Sun

发明人： Yu Liao ,  Hongwei Song ,  Lingyan Sun

IPC分类号： G06F17/10

CPC分类号： H03H21/0012 ,  G11B20/10055 ,  G11B20/10462 ,  G11B2220/2516 ,  H03H21/0067

摘要： Various embodiments of the present invention provide systems and methods for reducing filter sensitivities. As an example, reduced sensitivity filter circuits are discussed that include a digital filter and a filter tap adaptation circuit. The digital filter is operable to filter a received input based at least in part on a plurality of filter taps, and to provide a filtered output. The filter tap adaptation circuit is operable to receive an error value and a weighting control value, and to adaptively calculate at least one of the filter taps using the error value and the weighting control value.

摘要翻译： 本发明的各种实施例提供了用于降低过滤器灵敏度的系统和方法。 作为示例，讨论了包括数字滤波器和滤波器抽头适配电路的降低灵敏度滤波器电路。 数字滤波器可操作以至少部分地基于多个滤波器抽头对接收到的输入进行滤波，并提供滤波输出。 滤波器抽头适配电路可操作以接收误差值和加权控制值，并且使用误差值和加权控制值自适应地计算滤波器抽头中的至少一个。

公开(公告)号：US08176399B2

公开(公告)日：2012-05-08

申请号：US12380237

申请日：2009-02-25

申请人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

发明人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

IPC分类号： H03M13/03

CPC分类号： H03M13/27 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2957 ,  H03M13/2987 ,  H03M13/3746 ,  H03M13/3905 ,  H03M13/4146 ,  H03M13/6331 ,  H03M13/6337

摘要： A system, method, and device for detecting short burst errors in a queue-based system is disclosed. A first detector performs a data detection on a first input data set at a first time and on a second input data set at a second time. A second detector performs a data re-detection on input data sets. A decoder decodes derivations of the outputs of the first and second detector. A short burst error detector may perform a short burst error detection on decoded data and erase any detected errors. An output data buffer stores and orders the decoded data for output.

摘要翻译： 公开了一种用于检测基于队列的系统中的短脉冲串错误的系统，方法和装置。 第一检测器在第一时间对第一输入数据集合和第二输入数据集进行数据检测。 第二检测器对输入数据集执行数据重新检测。 解码器解码第一和第二检测器的输出的导数。 短脉冲串错误检测器可对解码数据执行短脉冲串错误检测，并擦除任何检测到的错误。 输出数据缓冲器存储并排序解码数据进行输出。

公开(公告)号：US08054573B2

公开(公告)日：2011-11-08

申请号：US12663336

申请日：2008-10-27

申请人： George Mathew ,  Yuan Xing Lee ,  Hongwei Song ,  Jeffrey P. Grundvig ,  Viswanath Annampedu

发明人： George Mathew ,  Yuan Xing Lee ,  Hongwei Song ,  Jeffrey P. Grundvig ,  Viswanath Annampedu

IPC分类号： G11B5/60

CPC分类号： G11B5/59688 ,  G11B5/6029

摘要： Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium (278), and a SAM based fly-height adjustment circuit (214). The storage medium (278) includes a plurality of servo data regions (110) that each include a servo address mark (154). The SAM based fly-height adjustment circuit (214) receives the servo address mark (154) from the plurality of servo data regions (110) via the read/write head assembly (276), and calculates a first harmonics ratio (445) based on the received data. The first harmonics ratio (445) is compared with a second harmonics ratio (450) to determine an error (365) in the distance (295) between the read/write head assembly (276) and the storage medium (278).

摘要翻译： 本发明的各种实施例提供了用于确定飞行高度调节的系统和方法。 例如，本发明的各种实施例提供了包括存储介质，相对于存储介质（278）设置的读/写头组件和基于SAM的飞高调节电路（214））的存储设备。 存储介质（278）包括多个伺服数据区域（110），每个伺服数据区域包括伺服地址标记（154）。 基于SAM的飞高调整电路（214）经由读/写头组件（276）从多个伺服数据区（110）接收伺服地址标记（154），并且基于第一谐波比（445）计算 接收到的数据。 将第一谐波比（445）与第二谐波比（450）进行比较，以确定读/写头组件（276）和存储介质（278）之间的距离（295）中的误差（365）。

公开(公告)号：US07849385B2

公开(公告)日：2010-12-07

申请号：US12111255

申请日：2008-04-29

申请人： Weijun Tan ,  Hongwei Song ,  Shaohua Yang

发明人： Weijun Tan ,  Hongwei Song ,  Shaohua Yang

IPC分类号： H03M13/00

CPC分类号： G11B20/1816

摘要： The present invention provides systems and methods for detecting a media defect. A circuit providing a hard output and a soft output is used with the hard output and the soft output being combined and the product compared with a threshold. Based at least in part on the comparison, a media defect may be identified.

摘要翻译： 本发明提供了用于检测介质缺陷的系统和方法。 提供硬输出和软输出的电路与硬输出和软输出组合使用，并将产品与阈值进行比较。 至少部分地基于比较，可以识别媒体缺陷。

公开(公告)号：US07779325B2

公开(公告)日：2010-08-17

申请号：US11041694

申请日：2005-01-24

申请人： Hongwei Song

发明人： Hongwei Song

IPC分类号： H03M13/00

CPC分类号： G11B20/1803 ,  G06F11/1008 ,  H03M13/41 ,  H03M13/4146 ,  H03M13/4153 ,  H03M13/6502

摘要： A data detection and decoding system includes a SOVA channel detector that uses single parity (SOVASP) to improve the accuracy with which the detector estimates bits. Each column or row read back from the read channel constitutes a code word and each code word is encoded to satisfy single parity. Because the SOVASP channel detector detects whether each code word satisfies single parity, it is unnecessary to use both a column decoder and a row decoder in the channel decoder. Either the row decoder or the column decoder can be eliminated depending on whether bits are read back on a column-by-column basis or on a row-by-row basis. This reduction in components reduces hardware complexity and improves system performance. The output of the row or column decoder is received by a second detector that processes the output received from the decoder to recover the original information bits.

摘要翻译： 数据检测和解码系统包括使用单个奇偶校验（SOVASP）的SOVA信道检测器来提高检测器估计比特的精度。 从读取通道读回的每个列或行构成一个代码字，每个代码字被编码以满足单个奇偶校验。 因为SOVASP信道检测器检测每个码字是否满足单个奇偶校验，所以不必在信道解码器中使用列解码器和行解码器。 取决于是逐列还是逐行读取位是否可以排除行解码器或列解码器。 组件的这种减少降低了硬件复杂性并提高了系统性能。 行或列解码器的输出由处理从解码器接收的输出的第二检测器接收以恢复原始信息位。

公开(公告)号：US20100177430A1

公开(公告)日：2010-07-15

申请号：US12663336

申请日：2008-10-27

申请人： George Mathew ,  Yuan Xing Lee ,  Hongwei Song ,  Jeffrey P. Grundvig ,  Viswanath Annampedu

发明人： George Mathew ,  Yuan Xing Lee ,  Hongwei Song ,  Jeffrey P. Grundvig ,  Viswanath Annampedu

IPC分类号： G11B21/02

CPC分类号： G11B5/59688 ,  G11B5/6029

摘要： Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium (278), and a SAM based fly-height adjustment circuit (214). The storage medium (278) includes a plurality of servo data regions (110) that each include a servo address mark (154). The SAM based fly-height adjustment circuit (214) receives the servo address mark (154) from the plurality of servo data regions (110) via the read/write head assembly (276), and calculates a first harmonics ratio (445) based on the received data. The first harmonics ratio (445) is compared with a second harmonics ratio (450) to determine an error (365) in the distance (295) between the read/write head assembly (276) and the storage medium (278).

摘要翻译： 本发明的各种实施例提供了用于确定飞行高度调节的系统和方法。 例如，本发明的各种实施例提供了包括存储介质，相对于存储介质（278）设置的读/写头组件和基于SAM的飞高调节电路（214））的存储设备。 存储介质（278）包括多个伺服数据区域（110），每个伺服数据区域包括伺服地址标记（154）。 基于SAM的飞高调整电路（214）经由读/写头组件（276）从多个伺服数据区（110）接收伺服地址标记（154），并且基于第一谐波比（445）计算 接收到的数据。 将第一谐波比（445）与第二谐波比（450）进行比较，以确定读/写头组件（276）和存储介质（278）之间的距离（295）中的误差（365）。

公开(公告)号：US20100053787A1

公开(公告)日：2010-03-04

申请号：US12199379

申请日：2008-08-27

申请人： George Mathew ,  Yuan Xing Lee ,  Hongwei Song

发明人： George Mathew ,  Yuan Xing Lee ,  Hongwei Song

IPC分类号： G11B5/02

CPC分类号： G11B5/09 ,  G11B20/10194

摘要： Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide systems for on-the-fly estimation of write pre-compensation values. Such systems include a magnetic storage medium, a read/write head assembly disposed in relation to the magnetic storage medium, and an analog to digital converter that receives an analog signal from the read/write head assembly corresponding to a data set stored on the magnetic storage medium and provides a series of digital samples corresponding to the data set. The storage devices further include a read data processing circuit that receives the same series of digital samples and provides a user data output, and a pre-compensation value calculation circuit that receives the series of digital samples and provides an updated write pre-compensation value.

摘要翻译： 本发明的各种实施例提供了用于写入预补偿的系统和方法。 例如，本发明的各种实施例提供用于写入预补偿值的即时估计的系统。 这样的系统包括磁存储介质，相对于磁存储介质设置的读/写头组件和模数转换器，其从读/写头组件接收对应于存储在磁盘上的数据集的模拟信号 并提供与数据集相对应的一系列数字样本。 存储装置还包括读取数据处理电路，其接收相同系列的数字样本并提供用户数据输出，以及预补偿值计算电路，其接收一系列数字样本并提供更新的写入预补偿值。