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公开(公告)号：US08780476B2
公开(公告)日：2014-07-15
申请号：US13242983
申请日：2011-09-23
申请人： Jeffrey P. Grundvig
发明人： Jeffrey P. Grundvig
IPC分类号： G11B5/09
CPC分类号： G11B20/1403 , G11B5/5965 , G11B20/10222
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide clock generation systems that include: a first clock multiplier circuit, a second clock multiplier circuit, a modulus accumulator circuit, and a data clock phase control circuit. The first clock multiplier circuit is operable to multiply a reference clock by a first multiplier to yield a first domain clock, and the second clock multiplier circuit is operable to multiply the reference clock by a second multiplier to yield a second domain clock. The modulus accumulator circuit is operable to yield a value indicating a fractional amount of the second domain clock that an edge of the second domain clock is offset from a trigger signal. The data clock phase control circuit is operable to phase shift the second domain clock by a phase amount corresponding to the fractional amount.
摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，本发明的一些实施例提供了时钟产生系统，其包括：第一时钟乘法器电路，第二时钟乘法器电路，模数累加器电路和数据时钟相位控制电路。 第一时钟乘法器电路可操作以将参考时钟乘以第一乘法器以产生第一域时钟，并且第二时钟乘法器电路可操作以将参考时钟乘以第二乘法器以产生第二域时钟。 模数累加器电路可操作以产生指示第二域时钟的边缘与触发信号偏移的第二域时钟的分数量的值。 数据时钟相位控制电路可操作以将第二域时钟相移相应于分数量的相位量。
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公开(公告)号：US08699160B2
公开(公告)日：2014-04-15
申请号：US13281923
申请日：2011-10-26
CPC分类号： G11B27/36 , G11B5/59627 , G11B5/59688 , G11B20/10009 , G11B20/18 , G11B27/3072 , G11B2220/2516
摘要： Methods and apparatus are provided for validating a detection of RRO address marks. After a potential RRO address mark is detected, a disclosed RROAM validation metric evaluates the energy of the remaining RRO data bits in the servo sector, relative to a predefined energy threshold. In addition, the number of remaining RRO data bits in the servo sector is compared to an expected value. The detected RRO address mark is validated in an exemplary embodiment if the RROAM validation metric satisfies the predefined energy threshold and the proper number of remaining RRO data bits is detected in the servo sector. The potential RRO address mark can optionally be discarded if the potential RRO address mark is not validated.
摘要翻译： 提供了用于验证RRO地址标记检测的方法和装置。 在检测到潜在的RRO地址标记之后，所公开的RROAM验证度量相对于预定义的能量阈值来评估伺服扇区中的剩余RRO数据位的能量。 此外，将伺服扇区中的剩余RRO数据位的数量与预期值进行比较。 如果RROAM验证度量满足预定能量阈值并且在伺服扇区中检测到适当数量的剩余RRO数据位，则在示例性实施例中验证检测到的RRO地址标记。 如果潜在的RRO地址标记未被验证，则可以可选地丢弃潜在的RRO地址标记。
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3.发明申请STORAGE DEVICE HAVING CLOCK ADJUSTMENT CIRCUITRY WITH FIRMWARE-BASED PREDICTIVE CORRECTION 有权具有基于固定预测校正的时钟调整电路的存储设备公开(公告)号：US20130135766A1
公开(公告)日：2013-05-30
申请号：US13306320
申请日：2011-11-29
IPC分类号： G11B27/10
CPC分类号： G11B20/10509 , G11B20/10222 , G11B2220/20
摘要： A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.
摘要翻译： 硬盘驱动器或其他基于磁盘的存储设备包括存储盘，被配置为从存储盘读取数据并将数据写入存储盘的读/写头，以及耦合到读/写头并被配置为处理接收到的数据的控制电路 从读取/写入头提供。 控制电路包括时钟调整电路，其被配置为至少部分地基于通过检测存储盘表面上的定时模式获得的定时信息来产生用于调整时钟信号的参数的控制信号。 控制信号是利用至少一个预测校正控制环来产生的，其中时钟调整电路包括实现预测校正控制环路的至少一部分的预测控制固件。
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公开(公告)号：US20130107687A1
公开(公告)日：2013-05-02
申请号：US13281923
申请日：2011-10-26
IPC分类号： G11B27/36
CPC分类号： G11B27/36 , G11B5/59627 , G11B5/59688 , G11B20/10009 , G11B20/18 , G11B27/3072 , G11B2220/2516
摘要： Methods and apparatus are provided for validating a detection of RRO address marks. After a potential RRO address mark is detected, a disclosed RROAM validation metric evaluates the energy of the remaining RRO data bits in the servo sector, relative to a predefined energy threshold. In addition, the number of remaining RRO data bits in the servo sector is compared to an expected value. The detected RRO address mark is validated in an exemplary embodiment if the RROAM validation metric satisfies the predefined energy threshold and the proper number of remaining RRO data bits is detected in the servo sector. The potential RRO address mark can optionally be discarded if the potential RRO address mark is not validated.
摘要翻译： 提供了用于验证RRO地址标记检测的方法和装置。 在检测到潜在的RRO地址标记之后，所公开的RROAM验证度量相对于预定义的能量阈值来评估伺服扇区中的剩余RRO数据位的能量。 此外，将伺服扇区中的剩余RRO数据位的数量与预期值进行比较。 如果RROAM验证度量满足预定能量阈值并且在伺服扇区中检测到适当数量的剩余RRO数据位，则在示例性实施例中验证检测到的RRO地址标记。 如果潜在的RRO地址标记未被验证，则可以可选地丢弃潜在的RRO地址标记。
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公开(公告)号：US20120134043A1
公开(公告)日：2012-05-31
申请号：US12955821
申请日：2010-11-29
IPC分类号： G11B27/36
CPC分类号： G11B5/59661 , G11B20/10009 , G11B2020/1238 , G11B2020/1281
摘要： Various embodiments of the present invention provide systems and methods for determining a location of a spiral pattern. As an example, a location detection circuits is discussed that includes: a pattern detection circuit, a computation circuit, and a center determination circuit. The pattern detection circuit is operable to identify a subset of a series of data samples corresponding to a defined pattern, and to indicate a location of the identified subset of the series of data samples. The series of data samples corresponds to a spiral pattern. The computation circuit operable to sum an absolute value of each sample of the subset of the series of data samples to yield a sum. The center determination circuit operable to identify a location of the spiral pattern using the sum.
摘要翻译： 本发明的各种实施例提供用于确定螺旋图案位置的系统和方法。 作为示例，讨论了位置检测电路，其包括：模式检测电路，计算电路和中心确定电路。 模式检测电路可操作以识别与定义的模式相对应的一系列数据样本的子集，并且指示所识别的一系列数据样本的子集的位置。 一系列数据样本对应于螺旋图案。 所述计算电路可操作以对所述一系列数据样本的所述子集的每个样本的绝对值求和以产生和。 中心确定电路可操作以使用该和来识别螺旋图案的位置。
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公开(公告)号：US06587694B1
公开(公告)日：2003-07-01
申请号：US09404807
申请日：1999-09-24
IPC分类号： H04L2730
CPC分类号： H04M1/72502
摘要： Clocks between at least two wireless devices are synchronized to reduce the need to transmit synchronization signals over a wireless communication channel therebetween. Two wireless devices synchronize their respective clocks with each other when each are electrically coupled, e.g., during a cradle time when brought into physical contact with each other through charge contacts, e.g., to recharge a remote portable unit. The charge signal appearing at the charge contacts is driven to create a time duration marked by a start transition and an end transition in the charge signal. The number of clock pulses of each of the two wireless devices during the time duration is counted, and compared to determine the difference in clock speeds of the wireless devices. The frequency of the clock of at least one of the wireless devices is adjusted to bring the difference in the clock speeds within a predetermined threshold tolerance level.
摘要翻译： 在至少两个无线设备之间的时钟被同步以减少通过它们之间的无线通信信道发送同步信号的需要。 两个无线设备在每个电耦合时使其各自的时钟彼此同步，例如在通过充电触点进行物理接触的支架时间期间，例如为远程便携式单元充电。 驱动出现在充电触点处的充电信号以产生由充电信号中的开始转换和结束转换所标记的持续时间。 对持续时间内的两个无线设备中的每一个的时钟脉冲数进行计数，并进行比较以确定无线设备的时钟速度的差异。 调整至少一个无线设备的时钟的频率以使时钟速度的差异在预定的阈值容差水平内。
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7.发明授权Disk-based storage device with head position control responsive to detected inter-track interference 有权基于磁盘的存储设备，其具有响应于检测到的磁道间干扰的磁头位置控制公开(公告)号：US08773806B2
公开(公告)日：2014-07-08
申请号：US13368508
申请日：2012-02-08
IPC分类号： G11B21/02
CPC分类号： G11B5/59627 , G11B19/045
摘要： A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises an inter-track interference detector configured to process a signal read from at least a given track of the storage disk via the read/write head in order to detect interference in that signal from at least one other track of the storage disk. The control circuitry further comprises an inter-track interference based head position controller configured to adjust the positioning of the read/write head responsive to the detected interference.
摘要翻译： 硬盘驱动器或其他基于磁盘的存储设备包括存储盘，被配置为从存储盘读取数据并将数据写入存储盘的读/写头，以及耦合到读/写头并被配置为处理接收到的数据的控制电路 从读取/写入头提供给读/写头，并且控制读/写头相对于存储盘的定位。 控制电路包括轨道间干扰检测器，其被配置为经由读/写头处理从至少存储盘的给定轨道读取的信号，以便检测来自存储盘的至少一个其它轨道的该信号的干扰 。 控制电路还包括基于轨道间干扰的头部位置控制器，其被配置为响应于检测到的干扰来调整读/写头的位置。
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公开(公告)号：US08498071B2
公开(公告)日：2013-07-30
申请号：US13173088
申请日：2011-06-30
CPC分类号： G11B20/10435 , G11B5/59616 , G11B5/59627 , G11B19/045 , G11B2020/1282 , G11B2020/1287 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a servo address mark count circuit, a user sync mark count circuit, and an offset calculation circuit. The servo address mark count circuit is operable to provide: a first count corresponding to a first servo address mark within a first track of a storage medium, a second count corresponding to a second servo address mark within the first track, a third count corresponding to a third servo address mark within a second track of the storage medium, and a fourth count corresponding to a fourth servo address mark within the second track. The user sync mark count circuit is operable to provide: a fifth count corresponding to a first user sync mark within the first track, and to provide a sixth count corresponding to a second user sync mark within the second track. The offset calculation circuit is operable to calculate an offset between the first track and the second track based at least in part on the first count, the second count, the third count, the fourth count, the fifth count, and the sixth count.
摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，讨论了包括：伺服地址标记计数电路，用户同步标记计数电路和偏移计算电路的数据处理电路。 伺服地址标记计数电路可操作地提供：与存储介质的第一轨道内的第一伺服地址标记相对应的第一计数，对应于第一轨道内的第二伺服地址标记的第二计数，对应于 在存储介质的第二磁道内的第三伺服地址标记，以及对应于第二磁道内的第四伺服地址标记的第四计数。 用户同步标记计数电路可操作以提供：对应于第一轨道内的第一用户同步标记的第五计数，并且提供对应于第二轨道内的第二用户同步标记的第六计数。 偏移计算电路至少部分地基于第一计数，第二计数，第三计数，第四计数，第五计数和第六计数来计算第一轨道和第二轨道之间的偏移。
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公开(公告)号：US07929237B2
公开(公告)日：2011-04-19
申请号：US12147543
申请日：2008-06-27
CPC分类号： G11B20/14 , G11B20/10222 , G11B2020/1476 , G11B2020/1484 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for controlling access to a magnetic storage medium. As one example, a method for controlling access to a storage medium is disclosed that includes calculating a point to point error amount, and generating a incremental error value based at least in part on the point to point error amount. The incremental error value is applied incrementally across a defined number of clock cycles.
摘要翻译： 本发明的各种实施例提供了用于控制对磁存储介质的访问的系统和方法。 作为一个示例，公开了一种用于控制对存储介质的访问的方法，其包括计算点对点误差量，并且至少部分地基于点对点误差量生成增量误差值。 递增错误值在规定数量的时钟周期内逐步应用。
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公开(公告)号：US20110043938A1
公开(公告)日：2011-02-24
申请号：US12663355
申请日：2008-10-27
CPC分类号： G11B5/6029 , G11B5/59688
摘要： Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium.
摘要翻译： 本发明的各种实施例提供用于确定飞行高度变化的系统和方法。 例如，本发明的各种实施例提供了包括其上具有伺服数据的存储介质的存储设备。 相对于存储介质设置读/写头组件。 基于伺服的飞高调节电路经由读/写头组件接收伺服数据，并且基于接收到的数据计算第一谐波比，并将第一谐波比与二次谐波比进行比较，以确定第二谐波比之间的距离误差 读/写头组件和存储介质。
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