公开(公告)号：US07830710B2

公开(公告)日：2010-11-09

申请号：US12363084

申请日：2009-01-30

申请人： Tomohiro Kurozumi ,  Hironori Akamatsu ,  Katsuji Satomi

发明人： Tomohiro Kurozumi ,  Hironori Akamatsu ,  Katsuji Satomi

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C29/02 ,  G11C29/24 ,  G11C29/802 ,  G11C2029/1208 ,  G11C2029/4402

摘要： In a semiconductor memory device 100, a non-volatile element section 4 stores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information S3 is newly outputted by a redundancy rescue section, a rescue determination section 5 determines whether or not a main memory cell is to be rescued, based on storage information S4 stored in the non-volatile element section 4, and the rescue information S3 which is newly outputted. The non-volatile element section 4 renews the storage information based on a determination result from the rescue determination section 5. Thus, on the assumption that power is turned off each time a voltage condition is changed, the semiconductor memory device 100 is capable of determining whether or not the rescue is to be performed, based on results of testings performed under a plurality of voltage conditions.

摘要翻译： 在半导体存储器件100中，非易失性元件部分4将用于拯救主存储器单元所需的信息作为存储信息存储在非易失性元件中。 当救援信息S3由冗余救援部重新输出时，救援判定部5基于存储在非易失性部件4中的存储信息S4来判定是否要救出主存储器单元，并且救援信息 新输出的S3。 非易失性元件部分4基于来自救援判定部分5的确定结果来更新存储信息。因此，假设每当电压条件改变时电源被关闭，则半导体存储器件100能够确定 是否基于在多个电压条件下执行的测试结果来执行救援。

公开(公告)号：US20080091969A1

公开(公告)日：2008-04-17

申请号：US11998602

申请日：2007-11-30

申请人： Marefusa Kurumada ,  Hironori Akamatsu

发明人： Marefusa Kurumada ,  Hironori Akamatsu

IPC分类号： G06F11/00

CPC分类号： G11C29/808 ,  G11C29/812

摘要： The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32 and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLA65 and outputs defect information to a redundant signal line RA. The redundant memory macro 2A includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

摘要翻译： 本发明提供了一种通过在多个SRAM宏中共享冗余存储器宏来提高区域效率和修复效率的半导体集成电路。 多个存储器宏1A 1和1A 2中的每一个包括连接到字线WL 1至WL 32和位线的存储单元阵列1A-3和替代存储单元阵列的有缺陷位线的冗余电路 到正常位线和冗余位线BLA 65，并将缺陷信息输出到冗余信号线RA。 冗余存储器宏2A包括连接到冗余字线和冗余位线的冗余存储单元阵列，以及第一字线连接电路，其连接与要修复的存储器宏对应的字线，并断开对应于 来自冗余字线的正常内存宏。

公开(公告)号：US06950362B2

公开(公告)日：2005-09-27

申请号：US10686826

申请日：2003-10-15

申请人： Marefusa Kurumada ,  Hironori Akamatsu

发明人： Marefusa Kurumada ,  Hironori Akamatsu

IPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C29/04 ,  G11C29/12 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/14 ,  G11C2207/065

摘要： A semiconductor memory device capable of enhancing a production yield is provided. A dummy control circuit activates a first dummy column including a plurality of dummy cells placed at a position close to a row decoder in a row direction and a second dummy column including a plurality of dummy cells placed at a position farthest from the row decoder in a row direction with a plurality of memory cells interposed between the first dummy column and the second dummy column, through first and second dummy word lines. A dummy column selector selects either one of a signal on a first dummy bit line connected to the first dummy column and a signal on a second dummy bit line connected to the second dummy column, and outputs the selected signal to an amplifier control circuit. The amplifier control circuit generates an amplifier startup signal with respect to an amplifier circuit based on a signal from the dummy column selector.

摘要翻译： 提供了能够提高生产率的半导体存储器件。 虚拟控制电路激活第一虚拟列，该第一虚拟列包括布置在行方向上靠近行解码器的位置的多个虚拟单元，以及第二虚拟列，其包括放置在距离行解码器最远的位置的多个虚拟单元 行方向，通过第一和第二伪字线插入在第一虚拟列和第二虚拟列之间的多个存储单元。 虚拟列选择器选择连接到第一虚拟列的第一虚拟位线上的信号和连接到第二虚拟列的第二虚拟位线上的信号之一，并将所选择的信号输出到放大器控制电路。 放大器控制电路基于来自虚拟列选择器的信号相对于放大器电路产生放大器启动信号。

公开(公告)号：US06919652B2

公开(公告)日：2005-07-19

申请号：US10035434

申请日：2002-01-04

申请人： Satoshi Takahashi ,  Takashi Hirata ,  Hironori Akamatsu ,  Yoshihide Komatsu ,  Koichi Sugimoto

发明人： Satoshi Takahashi ,  Takashi Hirata ,  Hironori Akamatsu ,  Yoshihide Komatsu ,  Koichi Sugimoto

IPC分类号： G06F1/26 ,  G06F13/40 ,  H01H3/26

CPC分类号： G06F1/266 ,  G06F13/4072 ,  Y10T307/50 ,  Y10T307/76 ,  Y10T307/937 ,  Y10T307/944

摘要： A network apparatus is provided, which allows another network apparatus to recognize the disconnection with reliability, if a power supply to the network apparatus is interrupted. A control unit operating with a first power supply outputs a first signal, which is level-converted and supplied as a second signal to an intermediate potential supply unit operating with a second power supply. In the intermediate potential supply unit, a switch receives a reset signal as a switch signal and outputs, when the power supply is interrupted, a ground potential to a driver instead of the second signal. As a result, an intermediate potential supplied to a cable is forcibly set to the ground potential.

摘要翻译： 如果网络设备的电源中断，则提供一种网络设备，其允许另一网络设备以可靠性识别该断开。 与第一电源一起操作的控制单元输出第一信号，该第一信号被电平转换并作为第二信号提供给与第二电源一起操作的中间电位供应单元。 在中间电位供给单元中，开关接收复位信号作为开关信号，并且当电源中断时，输出对驱动器的接地电位而不是第二信号。 结果，提供给电缆的中间电势被强制设定为地电位。

公开(公告)号：US20050073885A1

公开(公告)日：2005-04-07

申请号：US10714588

申请日：2003-11-14

申请人： Toshikazu Suzuki ,  Hironori Akamatsu

发明人： Toshikazu Suzuki ,  Hironori Akamatsu

IPC分类号： G11C11/413 ,  G11C7/08 ,  G11C7/14 ,  G11C11/417 ,  G11C11/419 ,  G11C29/04 ,  G11C11/34

CPC分类号： G11C7/14 ,  G11C7/08 ,  G11C7/227 ,  G11C11/417

摘要： A semiconductor memory device capable of accurately simulating a read-out timing of a memory cell and enhancing a production yield is provided. A dummy column selector is placed so as to be connected to dummy bit lines, and a plurality of dummy cells driving the dummy bit lines are placed at positions farthest in a column direction on a memory array from the side where an amplifier circuit is placed. This configuration allows a timing for driving the bit lines by the memory cells that are placed similarly at positions farthest from the amplifier circuit to be simulated accurately, thus enabling the generation of an amplifier startup signal without delay. Furthermore, a plurality of dummy word lines respectively connected to the plurality of dummy columns allow for readily switching from a dummy cell with a defect to a normal dummy cell.

公开(公告)号：US06604201B1

公开(公告)日：2003-08-05

申请号：US09428277

申请日：1999-10-27

申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

IPC分类号： G06F132

CPC分类号： H04L12/12 ,  Y02D50/20 ,  Y02D50/40

摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.

摘要翻译： 连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。 网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。 每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。 省电模式设置装置接收存储在网络信息存储器上的网络信息。 如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些 部分进入省电模式。

公开(公告)号：US06404370B2

公开(公告)日：2002-06-11

申请号：US09828936

申请日：2001-04-10

申请人： Yutaka Terada ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Takashi Hirata ,  Yoshihide Komatsu

发明人： Yutaka Terada ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Takashi Hirata ,  Yoshihide Komatsu

IPC分类号： H03M300

CPC分类号： H04L12/40052 ,  H04L12/40032

摘要： A semiconductor integrated circuit includes receiver, potential sensor and output fixing circuit. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing circuit fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level. In this configuration, once the variation in the in-phase potential of the differential signal has reached the predetermined level, the output of the receiver is fixed at the certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not supplied to the next stage like a digital section.

摘要翻译： 半导体集成电路包括接收器，电位传感器和输出固定电路。 接收机接收通过双绞信号线发送的差分信号，并根据差分信号输出信号。 电位传感器检测通过双绞线传输的差分信号的同相电位变化。 如果由电位传感器感测到的变化量等于或大于预定水平，则输出定影电路将接收器的输出固定在一定值。 在该配置中，一旦差分信号的同相电位的变化已经达到预定电平，则接收器的输出被固定在该特定值。 因此，即使接收器由于同相电位变化而错误地操作，接收机的错误输出也不像数字部分那样被提供给下一个级。

公开(公告)号：US06329843B1

公开(公告)日：2001-12-11

申请号：US09684979

申请日：2000-10-10

申请人： Takashi Hirata ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Yutaka Terada ,  Yoshihide Komatsu

发明人： Takashi Hirata ,  Hironori Akamatsu ,  Satoshi Takahashi ,  Yutaka Terada ,  Yoshihide Komatsu

IPC分类号： H03K190175

CPC分类号： H04L25/028 ,  H04L25/0276

摘要： A current driver, a common mode voltage monitoring circuit and a current compensator are provided to drive a twisted pair cable, which is made up of two signal lines coupled to a terminal bias voltage through respective terminal resistors. The common mode voltage monitoring circuit monitors a difference between a common mode voltage of the twisted pair cable and a supply voltage level for the current driver. And the current compensator is coupled to the twisted pair cable to compensate for an output current of the current driver in accordance with a result of monitoring performed by the common mode voltage monitoring circuit. If the current driver has decreased its current drivability due to a drop of the supply voltage level of the current driver or a variation in the common mode voltage of the twisted pair cable, then the current compensator compensates for the decrease. Thus, the current driver can continuously operate in a broad voltage range to supply a constant current.

摘要翻译： 提供电流驱动器，共模电压监视电路和电流补偿器来驱动双绞线电缆，双绞线电缆由通过相应的终端电阻器耦合到端子偏置电压的两根信号线组成。 共模电压监视电路监视双绞线电缆的共模电压与当前驱动器的电源电压差之间的差异。 并且电流补偿器耦合到双绞线电缆，以根据共模电压监视电路执行的监视结果补偿电流驱动器的输出电流。 如果当前的驱动器由于当前驱动器的电源电压下降或双绞线的共模电压的变化而降低其电流驱动能力，则电流补偿器补偿减小。 因此，电流驱动器可以在宽电压范围内连续工作以提供恒定电流。

公开(公告)号：US06208567B1

公开(公告)日：2001-03-27

申请号：US09014775

申请日：1998-01-28

申请人： Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Toru Iwata ,  Keiichi Kusumoto ,  Satoshi Takahashi ,  Yutaka Terada ,  Takashi Hirata

发明人： Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Toru Iwata ,  Keiichi Kusumoto ,  Satoshi Takahashi ,  Yutaka Terada ,  Takashi Hirata

IPC分类号： G11C2900

CPC分类号： G01R31/3004 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

摘要翻译： 本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

公开(公告)号：US6119250A

公开(公告)日：2000-09-12

申请号：US83389

申请日：1998-05-22

申请人： Kazuko Nishimura ,  Hironori Akamatsu ,  Akira Matsuzawa ,  Mitsuyasu Ohta

发明人： Kazuko Nishimura ,  Hironori Akamatsu ,  Akira Matsuzawa ,  Mitsuyasu Ohta

IPC分类号： G01R31/30 ,  G01R31/317 ,  G11C29/00

CPC分类号： G01R31/31701 ,  G01R31/3004

摘要： A test-target circuit is constructed of circuit blocks each comprising low-Vth MOS transistors including address buffers and a timing generator. A test enable signal for indication of a test, an operation selection signal for indication of an operation, and a block selection signal used to select a desired circuit block are provided. A high-Vth NMOS and a high-Vth PMOS transistor are provided in order to provide to a test circuit one of detected currents of the circuit blocks that was selected by placing a block selection signal and the test enable signal in the state of HIGH.

摘要翻译： 测试目标电路由包括地址缓冲器和定时发生器的低Vth MOS晶体管的电路块构成。 提供了用于指示测试的测试使能信号，用于指示操作的操作选择信号和用于选择期望的电路块的块选择信号。 提供高Vth NMOS和高Vth PMOS晶体管，以便向测试电路提供通过放置块选择信号和测试使能信号处于HIGH状态而选择的电路块的检测电流中的一个。