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公开(公告)号：US07830710B2
公开(公告)日：2010-11-09
申请号：US12363084
申请日：2009-01-30
CPC分类号： G11C29/02 , G11C29/24 , G11C29/802 , G11C2029/1208 , G11C2029/4402
摘要： In a semiconductor memory device 100, a non-volatile element section 4 stores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information S3 is newly outputted by a redundancy rescue section, a rescue determination section 5 determines whether or not a main memory cell is to be rescued, based on storage information S4 stored in the non-volatile element section 4, and the rescue information S3 which is newly outputted. The non-volatile element section 4 renews the storage information based on a determination result from the rescue determination section 5. Thus, on the assumption that power is turned off each time a voltage condition is changed, the semiconductor memory device 100 is capable of determining whether or not the rescue is to be performed, based on results of testings performed under a plurality of voltage conditions.
摘要翻译： 在半导体存储器件100中，非易失性元件部分4将用于拯救主存储器单元所需的信息作为存储信息存储在非易失性元件中。 当救援信息S3由冗余救援部重新输出时，救援判定部5基于存储在非易失性部件4中的存储信息S4来判定是否要救出主存储器单元，并且救援信息 新输出的S3。 非易失性元件部分4基于来自救援判定部分5的确定结果来更新存储信息。因此，假设每当电压条件改变时电源被关闭，则半导体存储器件100能够确定 是否基于在多个电压条件下执行的测试结果来执行救援。
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2.发明授权公开(公告)号：US07315479B2
公开(公告)日：2008-01-01
申请号：US11439223
申请日：2006-05-24
申请人： Tomohiro Kurozumi , Masashi Agata , Osamu Ichikawa
发明人： Tomohiro Kurozumi , Masashi Agata , Osamu Ichikawa
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C29/802
摘要： A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.
摘要翻译： 执行相对于冗余存储器的缓解处理的浮动处理部包括多个具有移位寄存器电路（浮动信息存储部）的缺陷消除部。 移位寄存器电路串联连接，以便连续传输数据。 测试电路测试冗余存储器，并且串行输出释放信息以缓解有缺陷的单元。 浮动处理部使用其数据传送操作将补救信息存储到移位寄存器电路中。
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公开(公告)号：US20060268633A1
公开(公告)日：2006-11-30
申请号：US11439223
申请日：2006-05-24
申请人： Tomohiro Kurozumi , Masashi Agata , Osamu Ichikawa
发明人： Tomohiro Kurozumi , Masashi Agata , Osamu Ichikawa
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C29/802
摘要： A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.
摘要翻译： 执行相对于冗余存储器的缓解处理的浮动处理部包括多个具有移位寄存器电路（浮动信息存储部）的缺陷消除部。 移位寄存器电路串联连接，以便连续传输数据。 测试电路测试冗余存储器，并且串行输出释放信息以缓解有缺陷的单元。 浮动处理部使用其数据传送操作将补救信息存储到移位寄存器电路中。
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公开(公告)号：US20070280015A1
公开(公告)日：2007-12-06
申请号：US11806308
申请日：2007-05-31
CPC分类号： G11C29/26 , G11C29/4401 , G11C29/72 , G11C29/789 , G11C29/806
摘要： Each of a plurality of redundant memories includes a plurality of memory cells and is operable to be relieved when a defective cell exists. This plurality of redundant memories can operate independently of each other. A relief processing portion is shared by this plurality of redundant memories. A test circuit inspects the plurality of redundant memories. When the test circuit determines that a defective cell exists, the test circuit outputs relief information to relieve the defective cell. The relief processing portion has a plurality of defect relief portions each having a relief information storage portion operable to store the relief information and performs the processing of relieving the plurality of redundant memories.
摘要翻译： 多个冗余存储器中的每一个包括多个存储器单元，并且可操作以在存在有缺陷单元时被释放。 该多个冗余存储器可以彼此独立地操作。 浮雕处理部分由该多个冗余存储器共享。 测试电路检查多个冗余存储器。 当测试电路确定存在故障单元时，测试电路输出释放信息以减轻故障单元。 浮雕处理部分具有多个缺陷释放部分，每个缺陷释放部分具有可操作以存储浮雕信息的浮雕信息存储部分，并执行减轻多个冗余存储器的处理。
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公开(公告)号：US5218241A
公开(公告)日：1993-06-08
申请号：US738841
申请日：1991-07-31
申请人： Tomohiro Kurozumi
发明人： Tomohiro Kurozumi
IPC分类号： G11C8/10 , H03K19/0944
CPC分类号： H03K19/09448 , G11C8/10
摘要： An AND circuit having a first input terminal, a second input terminal and an output terminal, and is defined by a P-channel MOS FET, an N-channel MOS FET, a NPN bipolar transistor and a resistor. The P-channel MOS FET has a source connected to the first input terminal and a gate connected to the second input terminal. The N-channel MOS FET has a gate connected to the second input terminal, a source connected to the ground and a drain connected to the drain of the P-channel MOS FET. The transistor has a base connected to the drain of the P-channel MOS FET, and the collector-emitter thereof connected between an electric power supply line and the ground. The resistor is connected in series to the collector-emitter of the transistor. One end of the resistor is connected to the output terminal. The AND circuit has less MOS FETs so that the layout area can be reduced.
摘要翻译： AND电路具有第一输入端子，第二输入端子和输出端子，并且由P沟道MOS FET，N沟道MOS FET，NPN双极晶体管和电阻器限定。 P沟道MOS FET具有连接到第一输入端的源极和连接到第二输入端的栅极。 N沟道MOS FET具有连接到第二输入端子的栅极，连接到地的源极和连接到P沟道MOS FET的漏极的漏极。 晶体管具有连接到P沟道MOS FET的漏极的基极，并且其集电极 - 发射极连接在电源线和地之间。 电阻器串联连接到晶体管的集电极 - 发射极。 电阻的一端连接到输出端子。 AND电路具有较少的MOS FET，从而可以减小布局面积。
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公开(公告)号：US07782687B2
公开(公告)日：2010-08-24
申请号：US12252974
申请日：2008-10-16
申请人： Tomohiro Kurozumi
发明人： Tomohiro Kurozumi
IPC分类号： G11C29/00
CPC分类号： G11C29/842
摘要： In a semiconductor device having a redundant memory, the area of the device is reduced and a time required to transfer relief information is reduced. Moreover, a transfer control of relief information is facilitated. A first relief information storing unit stores relief information for relieving a redundant memory having a defective cell. A plurality of redundant memories share a second relief information storing unit. The second relief information storing unit is connected in series to the first relief information storing unit. The relief information is transferred from the first relief information storing unit to the second relief information storing unit.
摘要翻译： 在具有冗余存储器的半导体器件中，器件的面积减小，并且减少传递浮雕信息所需的时间。 此外，促进了救济信息的转移控制。 第一释放信息存储单元存储用于减轻具有缺陷单元的冗余存储器的释放信息。 多个冗余存储器共享第二释放信息存储单元。 第二救济信息存储单元与第一救济信息存储单元串联连接。 救济信息从第一救济信息存储单元传送到第二救济信息存储单元。
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7.发明授权Control systems having an address conversion device for controlling a cache memory and a cache tag memory 失效控制系统具有用于控制高速缓冲存储器的地址转换装置和高速缓存标签存储器
公开(公告)号：US5584003A
公开(公告)日：1996-12-10
申请号：US575265
申请日：1995-12-20
CPC分类号： G06F12/1054
摘要： A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time. Further, this address conversion device controls a reading operation of the data stored in the cache memory by reading the physical address and the tag address at substantially the same time and by using a second control signal generated by the hit-signal generating circuit in synchronization with the word selecting signal. Moreover, the address conversion device controls the reading of data from the cache memory and the production of a cache hit signal, which is generated when the physical address matches the logical address. Accordingly, a high-performance system is achieved.
摘要翻译： 用于控制高速缓存标签存储器的控制系统具有地址转换装置，其包括用于存储逻辑地址的关联存储器，用于存储物理地址的随机存取存储器和用于产生命中信号的命中信号产生电路，字选择信号 和至少一个控制信号。 命中信号指示在存储在关联存储器中的逻辑地址与输入逻辑地址之间发生命中。 地址转换装置通过使用由命中信号发生电路产生的控制信号与存储在存储器中的物理地址的读取操作中使用的字选择信号同步地控制存储在高速缓存标签存储器中的标签地址的读取操作 随机访问存储器，使得物理地址和标签地址在基本相同的时间被读取。 此外，该地址转换装置通过在同一时间读取物理地址和标签地址来控制存储在高速缓冲存储器中的数据的读取操作，并且通过使用由命中信号发生电路产生的第二控制信号与 字选择信号。 此外，地址转换装置控制从高速缓冲存储器的数据的读取和当物理地址与逻辑地址匹配时产生的高速缓存命中信号的产生。 因此，实现了高性能的系统。
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公开(公告)号：US20100195424A1
公开(公告)日：2010-08-05
申请号：US12363084
申请日：2009-01-30
CPC分类号： G11C29/02 , G11C29/24 , G11C29/802 , G11C2029/1208 , G11C2029/4402
摘要： In a semiconductor memory device 100, a non-volatile element section 4 stores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information S3 is newly outputted by a redundancy rescue section, a rescue determination section 5 determines whether or not a main memory cell is to be rescued, based on storage information S4 stored in the non-volatile element section 4, and the rescue information S3 which is newly outputted. The non-volatile element section 4 renews the storage information based on a determination result from the rescue determination section 5. Thus, on the assumption that power is turned off each time a voltage condition is changed, the semiconductor memory device 100 is capable of determining whether or not the rescue is to be performed, based on results of testings performed under a plurality of voltage conditions.
摘要翻译： 在半导体存储器件100中，非易失性元件部分4将用于拯救主存储器单元所需的信息作为存储信息存储在非易失性元件中。 当救援信息S3由冗余救援部重新输出时，救援判定部5基于存储在非易失性部件4中的存储信息S4来判定是否要救出主存储器单元，并且救援信息 新输出的S3。 非易失性元件部分4基于来自救援判定部分5的确定结果来更新存储信息。因此，假设每当电压条件改变时电源被关闭，则半导体存储器件100能够确定 是否基于在多个电压条件下执行的测试结果来执行救援。
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公开(公告)号：US07539071B2
公开(公告)日：2009-05-26
申请号：US11806308
申请日：2007-05-31
IPC分类号： G11C7/00
CPC分类号： G11C29/26 , G11C29/4401 , G11C29/72 , G11C29/789 , G11C29/806
摘要： Each of a plurality of redundant memories includes a plurality of memory cells and is operable to be relieved when a defective cell exists. This plurality of redundant memories can operate independently of each other. A relief processing portion is shared by this plurality of redundant memories. A test circuit inspects the plurality of redundant memories. When the test circuit determines that a defective cell exists, the test circuit outputs relief information to relieve the defective cell. The relief processing portion has a plurality of defect relief portions each having a relief information storage portion operable to store the relief information and performs the processing of relieving the plurality of redundant memories.
摘要翻译： 多个冗余存储器中的每一个包括多个存储器单元，并且可操作以在存在有缺陷单元时被释放。 该多个冗余存储器可以彼此独立地操作。 浮雕处理部分由该多个冗余存储器共享。 测试电路检查多个冗余存储器。 当测试电路确定存在故障单元时，测试电路输出释放信息以减轻故障单元。 浮雕处理部分具有多个缺陷释放部分，每个缺陷释放部分具有可操作以存储浮雕信息的浮雕信息存储部分，并执行减轻多个冗余存储器的处理。
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公开(公告)号：US20090097334A1
公开(公告)日：2009-04-16
申请号：US12252974
申请日：2008-10-16
申请人： Tomohiro KUROZUMI
发明人： Tomohiro KUROZUMI
CPC分类号： G11C29/842
摘要： In a semiconductor device having a redundant memory, the area of the device is reduced and a time required to transfer relief information is reduced. Moreover, a transfer control of relief information is facilitated. A first relief information storing unit stores relief information for relieving a redundant memory having a defective cell. A plurality of redundant memories share a second relief information storing unit. The second relief information storing unit is connected in series to the first relief information storing unit. The relief information is transferred from the first relief information storing unit to the second relief information storing unit.
摘要翻译： 在具有冗余存储器的半导体器件中，器件的面积减小，并且减少传递浮雕信息所需的时间。 此外，促进了救济信息的转移控制。 第一释放信息存储单元存储用于减轻具有缺陷单元的冗余存储器的释放信息。 多个冗余存储器共享第二释放信息存储单元。 第二救济信息存储单元与第一救济信息存储单元串联连接。 救济信息从第一救济信息存储单元传送到第二救济信息存储单元。
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