-
61.发明授权Mechanisms for efficient message passing with copy avoidance in a distributed system using advanced network devices 有权使用高级网络设备的分布式系统中有效的消息传递与避免复制的机制公开(公告)号：US07089289B1
公开(公告)日：2006-08-08
申请号：US09619051
申请日：2000-07-18
IPC分类号： G06F15/167 , G06F15/16 , G06F13/28
CPC分类号： G06F13/28
摘要： An efficient mechanism for sending messages without the use of intermediate copies (i.e. without the staging of data) is provided. In particular an interface specification which allows use users of a transport protocol is defined so as to lend itself to efficient implementations. The interface specification is a complete and robust set of user functions usable within systems desiring reliable and efficient zero copy transport protocols. Two methods are provided to accomplish the implementation of an efficient zero copy protocol. The first method is especially useful in systems where the network device has limited capabilities in terms of hardware, message fragmentation and message reassembly. An additional RDRAM memory allows data to reside in an adapter while handshake operations take place between an adapter and a node so as to specify the final destination of the data. The second method takes advantage of network devices with advanced features which are exploited for maximum efficiency.
摘要翻译： 提供了一种用于在不使用中间副本（即，不进行数据分段）的情况下发送消息的有效机制。 特别地，允许使用传输协议的用户的接口规范被定义为使其能够有效地实现。 接口规范是一个完整和强大的用户功能集合，可在系统中使用，可靠和高效的零拷贝传输协议。 提供了两种方法来实现有效的零拷贝协议。 第一种方法在系统中特别有用，其中网络设备在硬件，消息分段和消息重组方面具有有限的能力。 另外的RDRAM内存允许数据驻留在适配器中，而握手操作会在适配器和节点之间进行，以便指定数据的最终目的地。 第二种方法利用具有高效能的网络设备，以最大限度地提高效率。
-
公开(公告)号：US06782464B2
公开(公告)日：2004-08-24
申请号：US09906860
申请日：2001-07-17
IPC分类号： G06F1200
CPC分类号： G06F12/0284
摘要： Communication between different entities of a computing environment is facilitated by an address mapping capability. Messages are sent between the entities to have desired tasks performed. Instead of providing within the messages the actual non-logical addresses (e.g., virtual, real addresses) used to perform the tasks, logical addresses are provided. The logical addresses are then mapped to the non-logical addresses. Each logical address can map to a plurality of non-logical addresses.
摘要翻译： 通过地址映射能力促进了计算环境的不同实体之间的通信。 在实体之间发送消息以执行所需的任务。 代替在消息内提供用于执行任务的实际非逻辑地址（例如，虚拟，真实地址），提供逻辑地址。 然后将逻辑地址映射到非逻辑地址。 每个逻辑地址可映射到多个非逻辑地址。
-
63.发明授权公开(公告)号：US08275963B2
公开(公告)日：2012-09-25
申请号：US12024486
申请日：2008-02-01
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译： 分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。 处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成 从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。 数据通过连接独立于处理器的两个节点的连接机制进行传输。
-
64.发明授权Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture 有权通过在指令集体系结构中执行AMM存储指令来执行异步存储器移动（AMM）公开(公告)号：US07958327B2
公开(公告)日：2011-06-07
申请号：US12024494
申请日：2008-02-01
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system with a processor and memory includes an instruction set architecture (ISA) that provides an asynchronous memory move (AMM) store (ST) instruction. When the processor executes the AMM ST instruction, the processor performs a series of functions, which initiates an asynchronous memory move (AMM) operation. The AMM ST instruction moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) performing a move of the data in virtual address space utilizing a source effective address that is memory mapped to the first memory location and a destination effective address that is memory mapped to the second memory location. When the move is completed in the virtual address space, the AMM operation performs the physical move of the data to the second memory location outside the processor core, without processor involvement.
摘要翻译： 具有处理器和存储器的数据处理系统包括提供异步存储器移动（AMM）存储（ST）指令的指令集架构（ISA）。 当处理器执行AMM ST指令时，处理器执行一系列功能，其启动异步存储器移动（AMM）操作。 AMM ST指令通过以下方式将数据从具有第一实际地址的第一存储器位置移动到具有第二实际地址的第二存储器位置：（a）使用存储器映射的源有效地址来执行虚拟地址空间中的数据移动 到第一存储器位置和存储器映射到第二存储器位置的目的地有效地址。 当在虚拟地址空间中完成移动时，AMM操作将数据物理移动到处理器核心外部的第二存储器位置，而无需处理器参与。
-
公开(公告)号：US07941627B2
公开(公告)日：2011-05-10
申请号：US12024674
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
摘要翻译： 指令集架构（ISA）包括异步存储器移动（AMM）同步（SYNC）指令。 当数据处理系统的处理器执行AMM SYNC指令时，处理器防止随后接收/执行的AMM ST指令产生的AMM操作进入存储器子系统内的AMM操作的数据移动部分，直到完成所有正在进行的存储器 内存子系统和结构中的访问操作。 AMM操作不等待正常的屏障操作。 处理器将与启动AMM操作相关的信息转发到异步存储器移动器逻辑，并且将逻辑信号发送到不进行AMM操作，直到AMM SYNC完成为止。
-
公开(公告)号：US07813369B2
公开(公告)日：2010-10-12
申请号：US11017406
申请日：2004-12-20
申请人： Robert S. Blackmore , Fu Chung Chang , Piyush Chaudhary , Kevin J. Gildea , Jason E. Goscinski , Rama K. Govindaraju , Donald G. Grice , Leonard W. Helmer, Jr. , Patricia E. Heywood , Peter H. Hochschild , John S. Houston , Chulho Kim , Steven J. Martin
发明人： Robert S. Blackmore , Fu Chung Chang , Piyush Chaudhary , Kevin J. Gildea , Jason E. Goscinski , Rama K. Govindaraju , Donald G. Grice , Leonard W. Helmer, Jr. , Patricia E. Heywood , Peter H. Hochschild , John S. Houston , Chulho Kim , Steven J. Martin
IPC分类号： G06F13/14
CPC分类号： H04L67/1097
摘要： In a multinode data processing system in which nodes exchange information over a network or through a switch, a structure and mechanism is provided within the realm of Remote Direct Memory Access (RDMA) operations in which DMA operations are present on one side of the transfer but not the other. On the side in which the transfer is not carried out in DMA fashion, transfer processing is carried out under program control; this is in contrast to the transfer on the DMA side which is characteristically carried out in hardware. Usage of these combination processes is useful in programming situations where RDMA is carried out to or from contiguous locations in memory on one side and where memory locations on the other side is noncontiguous. This split mode of transfer is provided both for read and for write operations.
摘要翻译： 在其中节点通过网络或通过交换机交换信息的多节点数据处理系统中，在远程直接存储器访问（RDMA）操作的领域内提供了结构和机制，其中DMA操作存在于传输的一侧，但是 不是其他的 在DMA方式不进行传输的一方，传送处理在程序控制下进行; 这与在硬件上进行特征性的DMA侧的传输相反。 这些组合过程的使用对于在一侧执行RDMA到存储器中的连续位置并且另一侧上的存储器位置不连续地执行RDMA的编程情况是有用的。 这种分离传输模式为读取和写入操作都提供。
-
公开(公告)号：US07689992B2
公开(公告)日：2010-03-30
申请号：US10877095
申请日：2004-06-25
IPC分类号： G06F9/46
CPC分类号： G06F9/526
摘要： Shared locks are employed for controlling a thread which extends across more than one protocol layer in a data processing system. The use of a counter is used as part of a data structure which makes it possible to implement shared locks across multiple layers. The use of shared locks avoids the processing overhead usually associated with lock acquisition and release. The thread which is controlled may be initiated in either an upper layer protocol or in a lower layer.
摘要翻译： 共享锁用于控制在数据处理系统中跨越多于一个协议层延伸的线程。 计数器的使用被用作数据结构的一部分，这使得可以跨多层实现共享锁。 共享锁的使用避免了通常与锁获取和释放相关的处理开销。 被控制的线程可以在上层协议或下层协议中启动。
-
68.发明申请ASYNCHRONOUS MEMORY MOVE ACROSS PHYSICAL NODES (DUAL-SIDED COMMUNICATION FOR MEMORY MOVE) 有权异常记忆移动物理名称（双面通信用于记忆移动）公开(公告)号：US20090198955A1
公开(公告)日：2009-08-06
申请号：US12024486
申请日：2008-02-01
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译： 分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。 处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成 从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。 数据通过连接独立于处理器的两个节点的连接机制进行传输。
-
公开(公告)号：US20090198934A1
公开(公告)日：2009-08-06
申请号：US12024613
申请日：2008-02-01
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system has a processor and a memory coupled to the processor and an asynchronous memory mover coupled to the processor. The asynchronous memory mover has registers for receiving a set of parameters from the processor, which parameters are associated with an asynchronous memory move (AMM) operation initiated by the processor in virtual address space, utilizing a source effective address and a destination effective address. The asynchronous memory mover performs the AMM operation to move the data from a first physical memory location having a source real address corresponding to the source effective address to a second physical memory location having a destination real address corresponding to the destination effective address. The asynchronous memory mover has an associated off-chip translation mechanism. The AMM operation thus occurs independent of the processor, and the processor continues processing other operations independent of the AMM operation.
摘要翻译： 数据处理系统具有耦合到处理器的处理器和存储器以及耦合到处理器的异步存储器移动器。 异步存储器移动器具有用于从处理器接收一组参数的寄存器，这些参数与虚拟地址空间中由处理器发起的异步存储器移动（AMM）操作相关联，利用源有效地址和目的地有效地址。 异步存储器移动器执行AMM操作以将来自具有与源有效地址相对应的源实际地址的第一物理存储器位置的数据移动到具有与目的地有效地址相对应的目的地实际地址的第二物理存储器位置。 异步存储器移动器具有相关的片外转换机制。 因此，AMM操作独立于处理器，并且处理器继续处理独立于AMM操作的其他操作。
-
公开(公告)号：US20090198917A1
公开(公告)日：2009-08-06
申请号：US12024674
申请日：2008-02-01
IPC分类号： G06F9/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
摘要翻译： 指令集架构（ISA）包括异步存储器移动（AMM）同步（SYNC）指令。 当数据处理系统的处理器执行AMM SYNC指令时，处理器防止随后接收/执行的AMM ST指令产生的AMM操作进入存储器子系统内的AMM操作的数据移动部分，直到完成所有正在进行的存储器 内存子系统和结构中的访问操作。 AMM操作不等待正常的屏障操作。 处理器将与启动AMM操作相关的信息转发到异步存储器移动器逻辑，并且将逻辑信号发送到不进行AMM操作，直到AMM SYNC完成为止。
-
-
-
-
-
-
-
-
-
搜索结果
73 条记录 (耗时 0.029 秒)