公开(公告)号：US20190384512A1

公开(公告)日：2019-12-19

申请号：US16555293

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F3/06

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

公开(公告)号：US20190378557A1

公开(公告)日：2019-12-12

申请号：US16549554

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Harish N. Venkata ,  Daniel B. Penney

IPC: G11C11/4091 ,  G11C11/4093 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to performing logic operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to the sensing circuitry and is configured to cause storing of a first operand in a first compute component storage location, transfer of the first operand to a second compute component storage location, and performance of a logical operation between the first operand in the second compute component storage location and a second operand sensed by the sense amplifier.

公开(公告)号：US20190311762A1

公开(公告)日：2019-10-10

申请号：US16448841

申请日：2019-06-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4093

Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.

公开(公告)号：US10418123B2

公开(公告)日：2019-09-17

申请号：US16119856

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Guy S. Perry ,  Harish N. Venkata ,  Glen E. Hush

IPC: G11C29/00

Abstract: Apparatuses and methods related to column repair in memory are described. The sensing circuitry of an apparatus can include a first sensing component, a second sensing component, and a third sensing component. The second sensing component can include a defective sense amplifier that is column repaired. The apparatus can include a controller configured to use the sensing circuitry to shift data from the first sensing component to the third sensing component by transferring the data through the second sensing component. The second sensing component can be physically located between the first sensing component and the third sensing component.

公开(公告)号：US10411919B2

公开(公告)日：2019-09-10

申请号：US16191169

申请日：2018-11-14

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Daniel B. Penney

IPC: H04L25/03 ,  G11C7/10 ,  H04L25/49 ,  G11C7/02 ,  G11C11/4096

Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

公开(公告)号：US20190259446A1

公开(公告)日：2019-08-22

申请号：US16051210

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4093 ,  G11C7/22 ,  G06F13/18 ,  G11C11/4076

Abstract: Devices and methods include utilizing memory including a group of storage elements, such as memory banks. A command interface is configured to receive a write command to write data to the memory. A data strobe is received to assist in writing the data to the memory. Phase division circuitry is configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory. Arbiter circuitry is configured to detect which phase of the plurality of phases captures a write start signal for the write command.

公开(公告)号：US20190259433A1

公开(公告)日：2019-08-22

申请号：US16051202

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10

Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.

公开(公告)号：US10387299B2

公开(公告)日：2019-08-20

申请号：US15214982

申请日：2016-07-20

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/0815 ,  G06F12/02 ,  G06F12/0855 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US20190235760A1

公开(公告)日：2019-08-01

申请号：US15883956

申请日：2018-01-30

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Liang Chen ,  Daniel B. Penney

IPC: G06F3/06

Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.

公开(公告)号：US10360951B1

公开(公告)日：2019-07-23

申请号：US15875651

申请日：2018-01-19

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C7/00 ,  G11C7/10 ,  G06F13/16 ,  G06F1/08 ,  G11C7/22 ,  G11C8/12

Abstract: Methods and systems for internal timing schemes are provided. A data strobe (DQS) signal is received at a memory device. The DQS signal is shifted in a negative direction relative to a clock of the memory device to cause a fail point of a flip flop of the memory device. After causing the fail point, the DQS signal is shifted in a positive direction relative to the clock. A transition edge of an internal write signal (IWS) is centered in a DQS period, such as a write preamble. The IWS indicates that a write command is to be captured. Moreover, centering the transition edge includes selectively delaying the IWS in the negative direction.