公开(公告)号：US20210294608A1

公开(公告)日：2021-09-23

申请号：US16824620

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F9/30 ,  G06N3/08

Abstract: The present disclosure is directed to systems and methods for a Processing-In-Memory Device that is configured to perform dot product calculations. A sequence control may be used to store data in a memory array according to an allocation pattern. The cells of the memory array may correspond to array elements of the data. The sequence control may apply another array of data to groups of elements within the memory array using the allocation pattern to perform dot product calculations. The dot product calculations may be used, for example, to implement a layer in a convolutional neural network.

公开(公告)号：US20210132689A1

公开(公告)日：2021-05-06

申请号：US16675168

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F3/01 ,  G06K9/00 ,  G02B27/00 ,  G02B27/01 ,  G06F3/0487

Abstract: An apparatus having a wearable structure, a computing device, a display, and a camera. The wearable structure is configured to be worn by a user and can be connected to the computing device, the display, and/or the camera. The computing device can be connected to the wearable structure, the display, and/or the camera. The display can be connected to the wearable structure, the computing device, and/or the camera. The display is configured to provide a graphical user interface (GUI). The camera can be connected to the computing device, the wearable structure, and/or the display. The camera is configured to capture eye movement of the user. A processor in the computing device is configured to identify one or more eye gestures from the captured eye movement. And, the processor is configured to control one or more parameters of the display and/or the GUI based on the identified eye gesture(s).

公开(公告)号：US20210073622A1

公开(公告)日：2021-03-11

申请号：US16887665

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06F12/06 ,  G06N3/04

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

公开(公告)号：US20200379919A1

公开(公告)日：2020-12-03

申请号：US16424420

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/1027 ,  H04L29/08

Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.

公开(公告)号：US12229060B2

公开(公告)日：2025-02-18

申请号：US17554400

申请日：2021-12-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F13/16 ,  G06F13/40

Abstract: A memory module having a plurality of memory chips, at least one controller (e.g., a central processing unit or special-purpose controller), and at least one interface device configured to communicate input and output data for the memory module. The input and output data bypasses at least one processor (e.g., a central processing unit) of a computing device in which the memory module is installed. And, the at least one interface device can be configured to communicate the input and output data to at least one other memory module in the computing device. Also, the memory module can be one module in a plurality of memory modules of a memory module system.

公开(公告)号：US12008460B2

公开(公告)日：2024-06-11

申请号：US17007588

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

CPC classification number: G06N3/063 ,  G06N3/049 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

公开(公告)号：US20240070107A1

公开(公告)日：2024-02-29

申请号：US17899531

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Troy Allen Manning

IPC: G06F13/42 ,  G06F13/32

CPC classification number: G06F13/4234 ,  G06F13/32

Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes memories that store data received from a host device. The memory device includes a memory interface to the host device. The memory device further includes one or more processing devices to perform, using a portion of the data stored in one or more of the memories, computations for a neural network. An output of the neural network is stored in one of the memories. The memory device has a controller that controls memory access by the host device and the processing devices to avoid a conflict. The memory device communicates with the host device over the memory interface using a DRAM bus protocol. This communication includes sending the output of the neural network to the host device.

公开(公告)号：US11836087B2

公开(公告)日：2023-12-05

申请号：US17132537

申请日：2020-12-23

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F12/08 ,  G06F12/0893

CPC classification number: G06F12/0893 ,  G06F2212/608

Abstract: The disclosed embodiments relate to per-process configuration caches in storage devices. A method is disclosed comprising initiating a new process, the new process associated with a process context; configuring a region in a memory device, the region associated with the process context, wherein the configuring comprises setting one or more cache parameters that modify operation of the memory device; and mapping the process context to the region of the memory device.

公开(公告)号：US20230010540A1

公开(公告)日：2023-01-12

申请号：US17878609

申请日：2022-08-01

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F9/38 ,  G06F9/30 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4091 ,  G06F15/80

Abstract: An example system implementing a processing-in-memory pipeline includes: a memory array to store a plurality of look-up tables (LUTs) and data; a control block coupled to the memory array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs; and a logic array coupled to the memory array and the control block, the logic array to perform, based on control inputs received from the control block, logic operations on the activated LUTs and the data.

公开(公告)号：US11436041B2

公开(公告)日：2022-09-06

申请号：US16592537

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/48 ,  G06F9/38 ,  G11C11/409 ,  G06F11/34 ,  G06F11/30

Abstract: Customized root processes for groups of applications in a computing device. A computing device (e.g., a mobile device) can monitor usage of applications. The device can then store data related to the usage of the applications, and group the applications into groups according to the stored data. The device can customize and execute a root process for a group of applications according to usage common to each application in the group. The device can generate patterns of prior executions shared amongst the applications in the group based on the stored data common to each application in the group, and execute the root process of the group according to the patterns. The device can receive a request to start an application from the group from a user of the device, and start the application upon receiving the request and by using the root process of the group of applications.