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65 条记录 (耗时 0.026 秒)

    Circuit for decoding 2T encoded binary signals
    62.
    发明授权
    Circuit for decoding 2T encoded binary signals 失效
    用于解码2T编码二进制信号的电路

    公开(公告)号：US5502408A

    公开(公告)日：1996-03-26

    申请号：US356076

    申请日：1994-12-14

    申请人： Werner Scholz

    发明人： Werner Scholz

    IPC分类号： G11B20/14 ,  G11B27/30 ,  H04L7/04 ,  H04L25/48 ,  H04L25/497 ,  G11C8/00

    CPC分类号： G11B20/10055 ,  G11B20/1403 ,  G11B27/3027 ,  H04L25/497 ,  H04L7/042

    摘要： A decoding circuit for 2T encoded binary signals, comprises: a data input terminal; a first D-type flip flop having an input coupled to the input terminal; a first exclusive OR gate having inputs coupled to the input terminal and an output of the first D-type flip flop; a shift register having an input coupled to an output of the exclusive OR gate; a second D-type flip flop having an input coupled to the shift register; and, a second exclusive OR gate having inputs coupled to an output of the second D-type flip flop and to a tap of the shift register, the second exclusive OR gate having an output at which decoded input signals are reconstituted. The second D-type flip flop may be a constituent stage of the shift register, the inputs of the second exclusive OR gate being coupled to adjacent taps of the shift register. At least one of the adjacent taps is the output of the constituent stage formed by the second D-type flip flop. A gate arrangement is coupled to a plurality of taps of the shift register for decoding a predetermined bit pattern in the input signal, for example, a synchronizing component of a digitally recorded video signal played back to the data input terminal. The consecutive taps of the shift register are chosen for equalizing a delay time between detection of the synchronizing component and the reconstituted video signal.

    摘要翻译： 一种用于2T编码二进制信号的解码电路，包括：数据输入端; 第一D型触发器，具有耦合到输入端的输入端; 具有耦合到输入端的输入和第一D型触发器的输出的第一异或门; 移位寄存器，具有耦合到异或门的输出的输入; 具有耦合到所述移位寄存器的输入的第二D型触发器; 以及具有耦合到所述第二D型触发器的输出和所述移位寄存器的抽头的输入的第二异或门，所述第二异或门具有重构解码输入信号的输出。 第二D型触发器可以是移位寄存器的组成级，第二异或门的输入被耦合到移位寄存器的相邻抽头。 相邻抽头中的至少一个是由第二D型触发器形成的构成级的输出。 门装置耦合到移位寄存器的多个抽头，用于对输入信号中的预定位模式进行解码，例如，将数字记录的视频信号的同步分量回放到数据输入端。 选择移位寄存器的连续抽头用于均衡同步分量的检测和重构的视频信号之间的延迟时间。

    Phase control circuit
    63.
    发明授权
    Phase control circuit 失效
    相位控制电路

    公开(公告)号：US4639687A

    公开(公告)日：1987-01-27

    申请号：US767198

    申请日：1985-08-12

    申请人： Werner Scholz

    发明人： Werner Scholz

    IPC分类号： H04N5/95 ,  G11B20/10 ,  H03L7/18 ,  H04N9/81 ,  H04N9/82 ,  H04N9/89 ,  H04N11/08 ,  H04N11/24 ,  H03L7/08

    CPC分类号： H04N9/81 ,  H04N11/08 ,  H04N9/8216 ,  H04N9/89

    摘要： The invention concerns a phase control circuit and a special digital controlled oscillator. According to the invention the digital controlled oscillator oscillates at two frequencies which are slightly above and slightly below the input frequency.

    摘要翻译： PCT No.PCT / EP84 / 00381 Sec。 371日期1985年8月12日 102（e）日期1985年8月12日PCT提交1984年12月1日PCT公布。 第WO85 / 02731号公报 1985年6月20日，本发明涉及一种相位控制电路和一种特殊的数字控制振荡器。 根据本发明，数字控制振荡器以略微高于并稍低于输入频率的两个频率振荡。

    Circuit for delaying a composite video signal by a line duration, particularly for use with a video record player
    65.
    发明授权
    Circuit for delaying a composite video signal by a line duration, particularly for use with a video record player 失效
    通过线路延迟延迟复合视频信号的电路，特别是与视频记录播放器一起使用

    公开(公告)号：US4101940A

    公开(公告)日：1978-07-18

    申请号：US753620

    申请日：1976-12-23

    申请人： Werner Scholz

    发明人： Werner Scholz

    IPC分类号： H04N9/86 ,  H04N9/893 ,  H04N5/79

    CPC分类号： H04N9/893

    摘要： A composite input video signal, having blanking intervals and including line sync pulses increasing the amplitude of the input signal, is applied to the circuit, is amplitude filtered, and is split into a BA-signal, which is fed to an adding stage, and line sync pulses which are fed to a monostable multivibrator which converts the line sync pulses into output pulses having an amplitude within the amplitude range of the filtered video signal, and these output pulses are also supplied to the adding stage. The output of the adding stage is applied to the input of a storage controlled by a timing pulse sequence from a timing pulse generator. The output pulses of the monostable multivibrator are supplied to a phase comparator having an input connected to the output of the storage through a gating device. The phase comparator supplies a variable to the timing pulse generator to control its frequency. The gating device transmits only during the line blanking interval A of the BA-signal, and thus transmits only the added multivibrator output pulses supplied to the input of the storage. The multivibrator output pulses and the video signal BA coincide, in time, at both the input and the output of the storage, so that the storage effects a delay exactly equal to the respective duration of a line.