公开(公告)号：US20100200906A1

公开(公告)日：2010-08-12

申请号：US12696544

申请日：2010-01-29

申请人： Masaru KIDOH ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

发明人： Masaru KIDOH ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

IPC分类号： H01L27/112 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film. The fourth insulating film is provided between the semiconductor pillar and the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 多层结构; 半导体柱; 第三绝缘膜; 和第四绝缘膜层。 多层结构设置在半导体衬底上，并且包括沿垂直于半导体衬底的主表面的第一方向堆叠的多个构成层叠体。 多个构成多层体中的每一个包括平行于主表面设置的电极膜，第一绝缘膜，设置在电极膜和第一绝缘膜之间的电荷存储层，以及设置在电荷存储层 电极膜。 半导体柱沿第一方向穿透多层结构。 第三绝缘膜设置在半导体柱和电极膜之间。 第四绝缘膜设置在半导体柱和电荷存储层之间。

公开(公告)号：US20090321813A1

公开(公告)日：2009-12-31

申请号：US12405522

申请日：2009-03-17

申请人： Masaru KIDOH ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Masaru KIDOH ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L27/11578 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/42348

摘要： A nonvolatile semiconductor memory device includes: a stacked body with a plurality of insulating films and electrode films alternately stacked therein, through which a through hole extending in the stacking direction is formed; a semiconductor pillar buried inside the through hole; and a charge storage layer located on both sides of each of the electrode films in the stacking direction and insulated from the electrode film and the semiconductor pillar.

摘要翻译： 非易失性半导体存储器件包括：具有交替堆叠的多个绝缘膜和电极膜的堆叠体，通过该堆叠体形成沿层叠方向延伸的通孔; 埋在通孔内的半导体柱; 以及电荷存储层，其位于层叠方向上的每个电极膜的两侧，并与电极膜和半导体柱绝缘。

公开(公告)号：US08916921B2

公开(公告)日：2014-12-23

申请号：US12705088

申请日：2010-02-12

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki

IPC分类号： H01L29/792 ,  H01L27/115 ,  G11C16/04

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582

摘要： A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness DEOT that satisfies the following relation (1). Dsio2

摘要翻译： 多个第一导电层在垂直方向上以一定间隔L设置，夹在其间的电介质。 设定一定间隔L使得第一电介质具有满足以下关系式（1）的等效氧化物厚度DEOT。 Dsio2

公开(公告)号：US08334561B2

公开(公告)日：2012-12-18

申请号：US12709702

申请日：2010-02-22

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L29/72

CPC分类号： H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11582

摘要： A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.

摘要翻译： 存储器串包括：第一半导体层，具有相对于衬底在垂直方向上延伸的多个柱状部分，以及连接多个柱状部分的下端的接合部分; 围绕所述第一半导体层的侧表面的电荷存储层; 以及围绕电荷存储层的侧表面并用作存储单元的控制电极的第一导电层。 选择晶体管包括：从柱状部分的上表面向上延伸的第二半导体层; 围绕所述第二半导体层的侧表面的绝缘层; 围绕所述绝缘层的侧表面并用作所述选择晶体管的控制电极的第二导电层; 以及形成在所述第二半导体层的上表面上并且包括硅锗的第三半导体层。

公开(公告)号：US08274108B2

公开(公告)日：2012-09-25

申请号：US12705231

申请日：2010-02-12

申请人： Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠体，包括交替层叠有多个电极膜的多个绝缘膜，所述电极膜被分割以形成沿第一方向排列的多个控制栅电极; 多个半导体柱沿堆叠体的堆叠方向排列，半导体柱沿着第一方向以矩阵构造排列，第二方向与第一方向相交以刺穿控制栅电极; 以及将所述半导体柱之一的下端部连接到所述半导体柱的另一个的下端部的连接部件，所述一个半导体柱的上端部与源极线连接，上端部 另一个半导体柱被连接到位线。 至少一些控制栅极电极在第二方向上被彼此相邻的两个半导体柱刺穿。 通过连接构件彼此连接的两个半导体柱穿透彼此不同的控制栅电极。

公开(公告)号：US08084807B2

公开(公告)日：2011-12-27

申请号：US12535847

申请日：2009-08-05

申请人： Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.

摘要翻译： 通过在与硅衬底的上表面正交的方向上交替堆叠用作控制栅极和电介质膜的电极膜来形成多层体。 在多层体中形成在字线方向上延伸的沟槽，并且在沟槽的内表面上形成记忆膜。 随后，将硅体埋在沟槽内，并且电荷存储膜和硅体在字线方向上分开以形成硅柱。 这简化了位线方向上的存储单元的配置，因此可以缩短硅柱的排列间距，减小每个存储单元的面积。

公开(公告)号：US08017993B2

公开(公告)日：2011-09-13

申请号：US12405522

申请日：2009-03-17

申请人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/42348

摘要： A nonvolatile semiconductor memory device includes: a stacked body with a plurality of insulating films and electrode films alternately stacked therein, through which a through hole extending in the stacking direction is formed; a semiconductor pillar buried inside the through hole; and a charge storage layer located on both sides of each of the electrode films in the stacking direction and insulated from the electrode film and the semiconductor pillar.

摘要翻译： 非易失性半导体存储器件包括：具有交替堆叠的多个绝缘膜和电极膜的堆叠体，通过该堆叠体形成沿层叠方向延伸的通孔; 埋在通孔内的半导体柱; 以及电荷存储层，其位于层叠方向上的每个电极膜的两侧，并与电极膜和半导体柱绝缘。

公开(公告)号：US07982261B2

公开(公告)日：2011-07-19

申请号：US12563832

申请日：2009-09-21

申请人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

发明人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion.

摘要翻译： 非易失性半导体存储器件包括在硅衬底上的第一层叠体，并且在其上设置第二层叠体。 第一堆叠体包括交替层叠有多个电极膜的多个绝缘膜，并且形成沿堆叠方向延伸的通孔的第一部分。 第二堆叠体包括交替层叠有多个电极膜的多个绝缘膜，并且形成通孔的第二部分。 在通孔的内表面上形成记忆膜，并且将硅柱埋在通孔的内部。 通孔的第二部分的中心轴线从第一部分的中心轴线偏移，并且第二部分的下端位于比第一部分的上部更低的位置。

公开(公告)号：US20110018050A1

公开(公告)日：2011-01-27

申请号：US12727830

申请日：2010-03-19

申请人： Tomoko FUJIWARA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoko FUJIWARA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/51 ,  H01L21/4763

CPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠结构单元; 连接部分半导体层电连接第一和第二半导体柱; 连接部分导电层，设置成与连接部分半导体层相对; 设置在所述第一半导体柱和所述半导体柱之间以及所述电极膜之间并且位于所述连接部分导电层和所述连接部半导体层之间的存储层和内部绝缘膜; 设置在所述存储层和每个所述电极膜之间的外部绝缘膜; 以及设置在存储层和连接部分导电层之间的连接部分外绝缘膜。 连接部外绝缘膜的膜厚比外绝缘膜的膜厚厚。

公开(公告)号：US20100207190A1

公开(公告)日：2010-08-19

申请号：US12705231

申请日：2010-02-12

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠体，包括交替层叠有多个电极膜的多个绝缘膜，所述电极膜被分割以形成沿第一方向排列的多个控制栅电极; 多个半导体柱沿层叠体的堆叠方向排列，半导体柱沿着第一方向排列成矩阵构造，第二方向与第一方向相交以刺穿控制栅电极; 以及将所述半导体柱之一的下端部连接到所述半导体柱的另一个的下端部的连接部件，所述一个半导体柱的上端部与源极线连接，上端部 另一个半导体柱被连接到位线。 至少一些控制栅极电极在第二方向上被彼此相邻的两个半导体柱刺穿。 通过连接构件彼此连接的两个半导体柱穿透相互不同的控制栅电极。