公开(公告)号：US08549183B2

公开(公告)日：2013-10-01

申请号：US12883781

申请日：2010-09-16

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US08473642B2

公开(公告)日：2013-06-25

申请号：US13198559

申请日：2011-08-04

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US08230119B2

公开(公告)日：2012-07-24

申请号：US12861439

申请日：2010-08-23

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F13/20

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20120089750A1

公开(公告)日：2012-04-12

申请号：US13316349

申请日：2011-12-09

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20110161703A1

公开(公告)日：2011-06-30

申请号：US13046345

申请日：2011-03-11

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F1/32

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US20080195780A1

公开(公告)日：2008-08-14

申请号：US11933126

申请日：2007-10-31

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Arraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Arraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/42

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US07360031B2

公开(公告)日：2008-04-15

申请号：US11171155

申请日：2005-06-29

申请人： Sridhar Lakshmanamurthy ,  Mason B. Cabot ,  Sameer Nanavati ,  Mark Rosenbluth

发明人： Sridhar Lakshmanamurthy ,  Mason B. Cabot ,  Sameer Nanavati ,  Mark Rosenbluth

IPC分类号： G06F12/02

CPC分类号： G06F13/1663 ,  G06F12/0835

摘要： Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O agents that issue atomic transactions to access and/or modify data stored in a shared memory space accessed via the memory interface unit. The host interface unit interfaces to a front-side bus (FSB) to which one or more processors may be coupled. In response to an atomic transaction issued by an I/O agent, the transaction is forked into two interdependent processes. Under one process, an inbound write transaction is injected into the host interface unit, which then drives the FSB to cause the processor(s) to perform a cache snoop. At the same time, an inbound read transaction is injected into the memory interface unit, which retrieves a copy of the data from the shared memory space. If the cache snoop identifies a modified cache line, a copy of that cache line is returned to the I/O agent; otherwise, the copy of the data retrieved from the shared memory space is returned.

摘要翻译： 使I / O代理能够在共享的，一致的存储器空间中执行原子操作的方法和装置。 该装置包括仲裁单元，主机接口单元和存储器接口单元。 仲裁单元向一个或多个发出原子事务的I / O代理提供接口以访问和/或修改存储在经由存储器接口单元访问的共享存储器空间中的数据。 主机接口单元与一个或多个处理器可以耦合到的前端总线（FSB）相连接。 为了响应由I / O代理发出的原子事务，事务被分成两个相互依赖的进程。 在一个过程中，入站写入事务被注入到主机接口单元中，然后驱动FSB使处理器执行缓存窥探。 同时，入站读取事务被注入到存储器接口单元中，该单元从共享存储器空间检索数据的副本。 如果缓存侦听器识别修改后的高速缓存行，则将该高速缓存行的副本返回给I / O代理; 否则，返回从共享存储空间检索的数据的副本。

公开(公告)号：US07210008B2

公开(公告)日：2007-04-24

申请号：US10741298

申请日：2003-12-18

申请人： Prashant R. Chandra ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo ,  Rohit Natarajan ,  Mark Rosenbluth

发明人： Prashant R. Chandra ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo ,  Rohit Natarajan ,  Mark Rosenbluth

IPC分类号： G06F12/00

CPC分类号： G06F13/1678

摘要： A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

摘要翻译： 存储器控制器，其包括到第一存储器的接口以及将存储器控制器耦合到至少一个处理器的总线的接口。 控制器还包括电路，响应于通过总线从至少一个处理器接收的读取和写入命令，将数据移位由至少一些读取和写入命令所标识的量。

公开(公告)号：US07185153B2

公开(公告)日：2007-02-27

申请号：US10742189

申请日：2003-12-18

申请人： Prashant R. Chandra ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo ,  Rohit Natarajan ,  Mark Rosenbluth

发明人： Prashant R. Chandra ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo ,  Rohit Natarajan ,  Mark Rosenbluth

IPC分类号： G06F12/00

CPC分类号： H04L69/166 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9042 ,  H04L49/9052 ,  H04L67/02 ,  H04L69/16 ,  H04L69/329 ,  H04L2012/5652

摘要： In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.

摘要翻译： 一般来说，在一个方面，本公开描述了一种在存储器中组装分组的方法。 该方法包括读取分组到多个分组的分组的第一分段中的数据，并向存储器控制器发出命令，该命令使得存储器控制器将读取的数据的子集移位并写入耦合到存储器控制器的存储器。 该方法还包括将剩余的读取数据保存为第一残余，检索包含在分组的第二段中的数据，以及将所检索的数据和第一残差的至少一部分写入存储器。

公开(公告)号：US20070022429A1

公开(公告)日：2007-01-25

申请号：US11190112

申请日：2005-07-25

申请人： Mark Rosenbluth ,  Sanjeev Jain ,  Gilbert Wolrich

发明人： Mark Rosenbluth ,  Sanjeev Jain ,  Gilbert Wolrich

IPC分类号： G06F9/46 ,  H02K17/00

CPC分类号： G06F9/52

摘要： In general, in one aspect, the disclosure describes a processor that includes multiple multi-threaded programmable units integrated on a single die. The die also includes circuitry communicatively coupled to the programmable units that reorders and grants lock requests received from the threads based on an order in which the threads requested insertion into a sequence of lock grants.

摘要翻译： 通常，在一个方面，本公开描述了一种处理器，其包括集成在单个管芯上的多个多线程可编程单元。 芯片还包括通信地耦合到可编程单元的电路，其基于线程请求插入到锁定授权序列中的顺序重新排序和授予从线程接收到的锁定请求。