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公开(公告)号：US20230345735A1
公开(公告)日：2023-10-26
申请号：US18214584
申请日：2023-06-27
Applicant: Microchip Technology incorporated
Inventor： Yaojian Leng
IPC: H10B53/30
Abstract: Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).
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62.发明公开公开(公告)号：US20230207615A1
公开(公告)日：2023-06-29
申请号：US17747302
申请日：2022-05-18
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L49/02 , H01L23/522 , H01L21/768
CPC classification number: H01L28/91 , H01L28/92 , H01L23/5226 , H01L21/76838
Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and a rounded insulator flange extending laterally outwardly and curving upwardly from the insulator cup, the rounded insulator flange covering an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the rounded insulator flange.
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公开(公告)号：US20230021192A1
公开(公告)日：2023-01-19
申请号：US17862693
申请日：2022-07-12
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L23/525 , H01L27/06
Abstract: An integrated circuit device includes an anti-fuse device. The anti-fuse device includes a cup-shaped bottom anti-fuse electrode, a cup-shaped anti-fuse insulator formed in an opening defined by the cup-shaped bottom anti-fuse electrode, and a top anti-fuse electrode formed in an opening defined by the cup-shaped anti-fuse insulator. A thickness of the cup-shaped anti-fuse insulator is less than 200 Å.
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64.发明授权公开(公告)号：US11552011B2
公开(公告)日：2023-01-10
申请号：US17308270
申请日：2021-05-05
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L23/522 , H01L21/768 , H01L49/02
Abstract: An integrated circuit structure includes a metal-insulator-metal (MIM) capacitor and a thin-film resistor (TFR) formed concurrently, using components of shared material layers. A first metal layer may be patterned to form lower components of an interconnect structure, MIM capacitor, and TFR, and a second metal layer may be patterned to form upper components of the interconnect structure, MIM capacitor, and TFR. A via layer may be deposited to form interconnect vias, a cup-shaped bottom electrode component of the MIM capacitor, and a pair of TFR contact vias for the TFR. An insulator layer may be patterned to form both an insulator for the MIM capacitor and an insulator cap over the TFR element.
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公开(公告)号：US20220399402A1
公开(公告)日：2022-12-15
申请号：US17409940
申请日：2021-08-24
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
Abstract: Carbon nanotube (CNT) memory cell elements and methods of forming CNT memory cell elements are provided. A CNT memory cell may comprise a CNT memory cell element, e.g., in combination with a transistor. A CNT memory cell element may include a metal/CNT layer/metal (M/CNT/M) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a metal interconnect layer. The M/CNT/M structure may be formed by a process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped CNT layer in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped CNT layer.
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Patent Agency Ranking
公开(公告)号：US20220393105A1
公开(公告)日：2022-12-08
申请号：US17379181
申请日：2021-07-19
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L45/00
Abstract: Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The MIM structure of the RRAM cell may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped insulator. The cup-shaped bottom electrode, or a component thereof (in the case of a multi-layer bottom electrode) may be formed concurrent with interconnect vias, e.g., by deposition of tungsten or other conformal metal.
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公开(公告)号：US20220157927A1
公开(公告)日：2022-05-19
申请号：US17233342
申请日：2021-04-16
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L49/02 , H01C7/00 , H01C17/075 , H01L23/532
Abstract: A thin film resistor (TFR) module may be formed in copper interconnect in an integrated circuit device. A pair of displacement-plated TFR heads may be formed by forming a pair of copper TFR head elements (e.g., damascene trench elements) spaced apart from each other in a dielectric region, and displacement plating a barrier region on each TFR head element to form a displacement-plated TFR head. A TFR element may be formed on the pair of displacement-plated TFR heads to define a conductive path between the pair of TFR head elements through the TFR element and through the displacement-plated barrier region on each metal TFR head. Conductive contacts may be formed connected to the pair of displacement-plated TFR heads. The displacement-plated barrier regions may protect the copper TFR heads from copper corrosion and/or diffusion, and may comprise CoWP, CoWB, Pd, CoP, Ni, Co, Ni—Co alloy, or other suitable material.
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68.发明申请公开(公告)号：US20190109186A1
公开(公告)日：2019-04-11
申请号：US16037941
申请日：2018-07-17
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
IPC: H01L49/02 , H01L23/522 , H01L23/532
Abstract: A damascene thin-film resistor (TFR), e.g., a damascene thin-film resistor module formed within a poly-metal dielectric (PMD) layer using a single added mask layer, and a method for manufacturing such a device, are disclosed. A method for manufacturing a TFR structure may include forming a pair of spaced-apart TFR heads formed as self-aligned silicide poly (salicide) structures, depositing a dielectric layer over the salicide TFR heads, patterning and etching a trench extending laterally over at least a portion of each salicide TFR head and exposing a surface of each salicide TFR heads is exposed, and depositing a TFR material into the trench and onto the exposed TFR head surfaces, to thereby form a TFR layer that bridges the pair of spaced-apart TFR heads.
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69.发明公开公开(公告)号：US20240215464A1
公开(公告)日：2024-06-27
申请号：US18600826
申请日：2024-03-11
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
CPC classification number: H10N70/841 , H10N70/066 , H10N70/24 , H10N70/245 , H10N70/826 , H10N70/8833
Abstract: Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The MIM structure of the RRAM cell may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped insulator. The cup-shaped bottom electrode, or a component thereof (in the case of a multi-layer bottom electrode) may be formed concurrently with interconnect vias, e.g., by deposition of tungsten or other conformal metal.
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公开(公告)号：US11937434B2
公开(公告)日：2024-03-19
申请号：US18214584
申请日：2023-06-27
Applicant: Microchip Technology Incorporated
Inventor： Yaojian Leng
Abstract: Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).
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