公开(公告)号：US20130105881A1

公开(公告)日：2013-05-02

申请号：US13646500

申请日：2012-10-05

申请人： James K. Kai ,  Vinod R. Purayath ,  George Matamis ,  Nima Mokhlesi ,  Cuong Trinh

发明人： James K. Kai ,  Vinod R. Purayath ,  George Matamis ,  Nima Mokhlesi ,  Cuong Trinh

IPC分类号： H01L29/788 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/66825

摘要： A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.

摘要翻译： 非易失性存储器制造工艺包括在形成隔离区之前形成完整的存储单元层堆叠。 存储单元层堆叠包括附加位置保持控制栅层。 在形成层堆叠列之后，附加的控制栅层将被并入在覆盖的控制栅极层和下面的中间介质层之间。 附加控制栅极层与柱之间的隔离区域自对准，同时将覆盖的控制栅极层蚀刻成用于与附加控制栅极层接触的线。 在一个实施例中，占位符控制栅极层有助于与上覆控制栅极层的接触点，使得选择栅极形成不需要控制栅极层与电荷存储层之间的接触。

公开(公告)号：US08400854B2

公开(公告)日：2013-03-19

申请号：US12694118

申请日：2010-01-26

申请人： Gen Pei ,  Lanlan Gu ,  Nima Mokhlesi ,  Idan Alrod ,  Eran Sharon ,  Itshak Afriat

发明人： Gen Pei ,  Lanlan Gu ,  Nima Mokhlesi ,  Idan Alrod ,  Eran Sharon ,  Itshak Afriat

IPC分类号： G11C29/04 ,  G11C29/06

CPC分类号： G11C16/3418 ,  G06F11/1072

摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.

摘要翻译： 非易失性存储系统基于性能数据预测哪些块（或其他存储单元）将变坏。 预测为坏的那些块中的用户数据可以被重新编程到其他块，并且预测为坏的块可以被进一步使用。

公开(公告)号：US08248859B2

公开(公告)日：2012-08-21

申请号：US12782957

申请日：2010-05-19

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer.

摘要翻译： 形成一组非易失性存储单元，其中控制栅极在浮置栅极，控制栅极和由隧道介电层分开的浮动栅极之间延伸。 控制门和浮动门之间的电子隧穿用于编程。 用于形成存储器阵列的过程从第一层形成奇数浮动栅极，并且从第二层形成偶数编号的浮动栅极。

公开(公告)号：US08164957B2

公开(公告)日：2012-04-24

申请号：US13178853

申请日：2011-07-08

申请人： Deepak Chandra Sekar ,  Nima Mokhlesi

发明人： Deepak Chandra Sekar ,  Nima Mokhlesi

IPC分类号： G11C16/04

CPC分类号： G11C5/146 ,  G11C16/10 ,  G11C16/26 ,  G11C2029/0409

摘要： Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

摘要翻译： 可以应用身体偏差来优化非易失性存储系统中的性能。 当从非易失性存储元件读取数据时，可以以自适应的方式设置体偏置以减少纠错和/或检测代码的错误计数。 此外，随着编程周期的增加，体偏置电平可以增加或减小。 此外，可以为芯片，平面，块和/或页面分别设置和应用身体偏置水平。 体偏置可以应用于通过控制提供给第一组NAND串的源极侧的第一电压和提供给p阱的第二电压来执行其操作的第一组NAND串。 没有执行操作的第二组NAND串的源极侧浮动或接收固定电压。

公开(公告)号：US08143156B2

公开(公告)日：2012-03-27

申请号：US11765866

申请日：2007-06-20

申请人： George Matamis ,  James Kai ,  Takashi Orimoto ,  Nima Mokhlesi

发明人： George Matamis ,  James Kai ,  Takashi Orimoto ,  Nima Mokhlesi

IPC分类号： H01L21/4763

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.

摘要翻译： 公开了高密度半导体器件及其制造方法。 利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。 可以处理第一组间隔件以提供平面和平行的侧壁。 可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。 第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。 根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

公开(公告)号：US20120039124A1

公开(公告)日：2012-02-16

申请号：US13280124

申请日：2011-10-24

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/26

摘要： In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.

摘要翻译： 在感测多状态非易失性存储器中的一组单元时，需要相对于不同分界阈值电平的多个感测周期来解决所有可能的多个存储器状态。 每个感测周期都有一个感测通道。 它还可以包括预感测通过或子周期，以识别其阈值电压低于当前正在被感测的分界阈值水平的单元。 这些是更高的电流单元，可以关闭以实现省电和减少源偏置误差。 通过将它们的相关位线锁定到地来关闭电池。 然后，重复感应通过将产生更准确的结果。 提供电路和方法来选择性地启用或禁用位线锁定和预感测，以便提高性能，同时确保感测操作不消耗超过最大电流电平。

公开(公告)号：US08097504B2

公开(公告)日：2012-01-17

申请号：US11768461

申请日：2007-06-26

申请人： Nima Mokhlesi ,  Jun Wan

发明人： Nima Mokhlesi ,  Jun Wan

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.

摘要翻译： 公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。 位线在两个分离的金属层的每一个中以4f间距形成，并且布置成在每个层之间交替。 在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

公开(公告)号：US20110235420A1

公开(公告)日：2011-09-29

申请号：US12732121

申请日：2010-03-25

申请人： Eran Sharon ,  Yan Li ,  Nima Mokhlesi

发明人： Eran Sharon ,  Yan Li ,  Nima Mokhlesi

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5624 ,  G11C2211/5631

摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.

摘要翻译： 公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。 公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。 公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。 可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。 可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。 可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。 交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

公开(公告)号：US20110225473A1

公开(公告)日：2011-09-15

申请号：US13113312

申请日：2011-05-23

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C29/52 ,  G11C16/04 ,  G11C16/26 ,  G06F11/07

CPC分类号： G11C16/3418 ,  G11C11/5642 ,  G11C16/0483

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元具有的耦合效应。

公开(公告)号：US07971127B2

公开(公告)日：2011-06-28

申请号：US11694951

申请日：2007-03-31

申请人： Henry Chin ,  Nima Mokhlesi

发明人： Henry Chin ,  Nima Mokhlesi

IPC分类号： H03M13/00 ,  H03M13/03

CPC分类号： G11C11/5642 ,  G06F11/1072 ,  G11C29/00

摘要： Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

摘要翻译： 使用迭代概率解码对非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 可以使用基于数据中的误差水平的可调节温度参数进行模拟退火。 模拟退火可以将随机性作为噪声引入到解码过程中。 此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。 引入一定程度的随机性增加了灵活性，允许在数据可能不可纠正的情况下可能更快的收敛时间和收敛。