利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

29 条记录 (耗时 0.024 秒)

    Self-Aligned Planar Flash Memory And Methods Of Fabrication
    1.
    发明申请
    Self-Aligned Planar Flash Memory And Methods Of Fabrication 审中-公开
    自对平面闪存及其制作方法

    公开(公告)号：US20130105881A1

    公开(公告)日：2013-05-02

    申请号：US13646500

    申请日：2012-10-05

    申请人： James K. Kai ,  Vinod R. Purayath ,  George Matamis ,  Nima Mokhlesi ,  Cuong Trinh

    发明人： James K. Kai ,  Vinod R. Purayath ,  George Matamis ,  Nima Mokhlesi ,  Cuong Trinh

    IPC分类号： H01L29/788 ,  H01L21/762 ,  H01L21/336

    CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/66825

    摘要： A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.

    摘要翻译： 非易失性存储器制造工艺包括在形成隔离区之前形成完整的存储单元层堆叠。 存储单元层堆叠包括附加位置保持控制栅层。 在形成层堆叠列之后，附加的控制栅层将被并入在覆盖的控制栅极层和下面的中间介质层之间。 附加控制栅极层与柱之间的隔离区域自对准，同时将覆盖的控制栅极层蚀刻成用于与附加控制栅极层接触的线。 在一个实施例中，占位符控制栅极层有助于与上覆控制栅极层的接触点，使得选择栅极形成不需要控制栅极层与电荷存储层之间的接触。

    Dielectric layer above floating gate for reducing leakage current
    3.
    发明授权
    Dielectric layer above floating gate for reducing leakage current 有权
    介质层上方浮栅为了减少漏电流

    公开(公告)号：US07919809B2

    公开(公告)日：2011-04-05

    申请号：US12170327

    申请日：2008-07-09

    申请人： Dana Lee ,  Henry Chin ,  James K. Kai ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis

    发明人： Dana Lee ,  Henry Chin ,  James K. Kai ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/1203

    摘要： A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.

    摘要翻译： 公开了一种包括一组非易失性存储元件的存储器系统。 给定的存储单元在浮动栅极上方具有电介质盖。 在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。 电介质盖减少了浮动栅极和控制栅极之间的漏电流。 电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。

    METHOD OF FORMING DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT
    8.
    发明申请
    METHOD OF FORMING DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT 有权
    形成用于降低泄漏电流的浮动栅上的介电层的方法

    公开(公告)号：US20100009503A1

    公开(公告)日：2010-01-14

    申请号：US12170321

    申请日：2008-07-09

    申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

    发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/28273

    摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

    摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

    Method of forming dielectric layer above floating gate for reducing leakage current
    9.
    发明授权
    Method of forming dielectric layer above floating gate for reducing leakage current 有权
    在浮栅上形成介质层以减少漏电流的方法

    公开(公告)号：US07915124B2

    公开(公告)日：2011-03-29

    申请号：US12170321

    申请日：2008-07-09

    申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

    发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L21/28273

    摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

    摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

    DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT
    10.
    发明申请
    DIELECTRIC LAYER ABOVE FLOATING GATE FOR REDUCING LEAKAGE CURRENT 有权
    用于降低泄漏电流的浮动门上的介电层

    公开(公告)号：US20100006915A1

    公开(公告)日：2010-01-14

    申请号：US12170327

    申请日：2008-07-09

    申请人： Dana Lee ,  Henry Chin ,  James K. Kai ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis

    发明人： Dana Lee ,  Henry Chin ,  James K. Kai ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/1203

    摘要： A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.

    摘要翻译： 公开了一种包括一组非易失性存储元件的存储器系统。 给定的存储单元在浮动栅极上方具有电介质盖。 在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。 电介质盖减少了浮动栅极和控制栅极之间的漏电流。 电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。