公开(公告)号：US20160267000A1

公开(公告)日：2016-09-15

申请号：US14641828

申请日：2015-03-09

Applicant: Oracle International Corporation

Inventor： John R. Rose ,  Victor Luchangco ,  David Dice

IPC: G06F11/36 ,  G06F9/46 ,  G06F9/44

CPC classification number: G06F11/3688 ,  G06F8/70 ,  G06F9/4484 ,  G06F9/466 ,  G06F9/467 ,  G06F11/30

Abstract: Approaches for more efficiently executing calls to native code from within a managed execution environment are described. The techniques involve attempting to execute a native call, such as a call to a C function from within Java code, using a single hardware transaction. Not only is the native code executed in a hardware transaction, but also various transitional operations needed for transitioning between managed execution mode and native execution mode. If the hardware transaction is successful, at least some of the operations that would normally be performed during transitions between modes may be omitted or simplified. If the hardware transaction is unsuccessful, the native calls may be performed as they normally would, outside of hardware transactions.

Abstract translation: 描述从管理的执行环境中更有效地执行对本地代码的调用的方法。 这些技术包括尝试使用单个硬件事务来执行本机调用，例如从Java代码中调用C函数。 本地代码不仅在硬件事务中执行，还包括在托管执行模式和本地执行模式之间转换所需的各种过渡操作。 如果硬件事务成功，则可以省略或简化在模式间转换期间通常执行的至少一些操作。 如果硬件事务不成功，则可以在硬件事务之外正常执行本机呼叫。

公开(公告)号：US09342380B2

公开(公告)日：2016-05-17

申请号：US13784965

申请日：2013-03-05

Applicant: Oracle International Corporation

Inventor： David Dice ,  Yosef Lev ,  Yujie Liu ,  Victor M. Luchangco ,  Mark S. Moir

IPC: G06F12/00 ,  G06F9/52 ,  G06F9/46

CPC classification number: G06F9/467 ,  G06F9/5027 ,  G06F9/528 ,  G06F2209/523

Abstract: Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.

Abstract translation: 事务读写器锁可以利用可用的硬件事务存储器（HTM）来简化读写器锁定算法的过程，并消除对类型稳定存储器的要求基于HTM的读写器锁可以包括客户端 - 提供的节点，每个节点表示一个保存（或希望获取）锁的线程和一个尾部指针。 读者和作者调用的锁定和解锁过程可以使用事务和非事务性访问的各种组合来访问列表中的尾部指针或特定节点，以将节点插入到列表中或从列表中删除节点。 在列表头部拥有一个节点的阅读器或写入器（或者只有其他读取器节点在其列表中的节点之前的读取器）可以访问代码或共享资源的关键部分。

公开(公告)号：US20150248310A1

公开(公告)日：2015-09-03

申请号：US14697510

申请日：2015-04-27

Applicant: Oracle International Corporation

Inventor： David Dice ,  Mark S. Moir

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/54

Abstract: In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.

Abstract translation: 在共享内存计算机系统中，线程可以使用共享内存彼此进行通信。 接收线程可以重复轮询消息目标位置以检测消息的传递。 这种轮询可能导致各种系统总线和/或其他互连上的高速缓存一致性业务和/或拥塞。 用于处理器间通信的方法可以通过减少执行的读取的数量和/或传递消息所需的高速缓存一致性消息的数量来减少这种总线流量。 该方法可以包括读取消息目标位置的值一次的线程，并且通过检测指示这种修改的处理器间消息（例如高速缓存一致性消息）来确定该值已被修改。 在支持事务内存的系统中，线程可以使用事务存储器原语来检测高速缓存一致性消息。 这可以通过启动事务，读取目标内存位置和旋转直到事务中止来完成。

公开(公告)号：US20140215157A1

公开(公告)日：2014-07-31

申请号：US13754700

申请日：2013-01-30

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Mark S. Moir ,  Paul N. Loewenstein ,  David Dice

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F9/30047 ,  G06F11/3037 ,  G06F11/3096 ,  G06F12/0831 ,  G06F2201/885

Abstract: A system and method for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. More specifically, the disclosed embodiments provide a system that notifies a waiting thread when a targeted store is directed to monitored memory locations. During operation, the system receives a targeted store which is directed to a specific cache in a shared-memory multiprocessor system. In response, the system examines a destination address for the targeted store to determine whether the targeted store is directed to a monitored memory location which is being monitored for a thread associated with the specific cache. If so, the system informs the thread about the targeted store.

Abstract translation: 用于在共享存储器多处理器中支持目标存储的系统和方法。 目标商店使得第一处理器能够将要存储在第二处理器的高速缓冲存储器中的高速缓存行推送。 这消除了对多个高速缓存相干操作的需要，以将高速缓存行从第一处理器传送到第二处理器。 更具体地，所公开的实施例提供了当目标商店被引导到被监视的存储器位置时通知等待线程的系统。 在操作期间，系统接收目标商店，其被定向到共享存储器多处理器系统中的特定高速缓存。 作为响应，系统检查目标商店的目的地地址，以确定目标商店是否被定向到被监视的与特定高速缓存相关联的线程的监视的存储器位置。 如果是这样，系统通知线程有关目标商店。

公开(公告)号：US12260267B2

公开(公告)日：2025-03-25

申请号：US18052890

申请日：2022-11-04

Applicant: Oracle International Corporation

Inventor： Alex Kogan ,  David Dice

IPC: G06F9/46 ,  G06F9/52

Abstract: A computer comprising multiple processors and non-uniform memory implements multiple threads that perform a lock operation using a shared lock structure that includes a pointer to a tail of a first-in-first-out (FIFO) queue of threads waiting to acquire the lock. To acquire the lock, a thread allocates and appends a data structure to the FIFO queue. The lock is released by selecting and notifying a waiting thread to which control is transferred, with the thread selected executing on the same processor socket as the thread controlling the lock. A secondary queue of threads is managed for threads deferred during the selection process and maintained within the data structures of the waiting threads such that no memory is required within the lock structure. If no threads executing on the same processor socket are waiting for the lock, entries in the secondary queue are transferred to the FIFO queue preserving FIFO order.

公开(公告)号：US12254900B2

公开(公告)日：2025-03-18

申请号：US18617546

申请日：2024-03-26

Applicant: Oracle International Corporation

Inventor： David Dice ,  Alex Kogan

IPC: G11B20/10 ,  G06F9/52 ,  G06F16/23 ,  G11B20/18 ,  G11C16/26

Abstract: A data object has a lock and a condition indicator associated with it. Based at least partly on detecting a first setting of the condition indicator, a reader stores an indication that the reader has obtained read access to the data object in an element of a readers structure and reads the data object without acquiring the lock. A writer detects the first setting and replaces it with a second setting, indicating that the lock is to be acquired by readers before reading the data object. Prior to performing a write on the data object, the writer verifies that one or more elements of the readers structure have been cleared.

公开(公告)号：US12254317B2

公开(公告)日：2025-03-18

申请号：US18418980

申请日：2024-01-22

Applicant: Oracle International Corporation

Inventor： David Dice ,  Alex Kogan

IPC: G06F12/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F12/0802 ,  G06F13/16

Abstract: A computer comprising one or more processors and memory may implement multiple threads that perform a lock operation using a data structure comprising an allocation field and a grant field. Upon entry to a lock operation, a thread allocates a ticket by atomically copying a ticket value contained in the allocation field and incrementing the allocation field. The thread compares the allocated ticket to the grant field. If they are unequal, the thread determines a number of waiting threads. If the number is above the threshold, the thread enters a long term wait operation comprising determining a location for long term wait value and waiting on changes to that value. If the number is below the threshold or the long term wait operation is complete, the thread waits for the grant value to equal the ticket to indicate that the lock is allocated.

公开(公告)号：US12124876B2

公开(公告)日：2024-10-22

申请号：US17169246

申请日：2021-02-05

Applicant: Oracle International Corporation

Inventor： David Dice ,  Alex Kogan

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5027 ,  G06F9/30145

Abstract: Compact and scalable mutual exclusion techniques are implemented for multiple executing threads. A thread may acquire a lock by swapping a pointer to the thread into a tail field of a lock data structure. If the swap operation returned a null value, then the lock is acquired. If the swap operation does not return a null value, then the thread may wait to obtain the lock from a predecessor thread. The thread may wait until a grant field in a data structure for the predecessor thread stores a pointer to the lock, signaling to the thread that the thread may acquire the lock.

公开(公告)号：US12079278B2

公开(公告)日：2024-09-03

申请号：US18183891

申请日：2023-03-14

Applicant: Oracle International Corporation

Inventor： Alex Kogan ,  David Dice ,  Shady Alaaeldin Mohamed Abdelkader Rabie Issa

IPC: G06F16/901 ,  G06F11/30 ,  G06F16/176

CPC classification number: G06F16/9024 ,  G06F11/3006 ,  G06F16/1774

Abstract: A computer comprising one or more processors and memory may implement multiple threads performing mutually exclusive lock acquisition operations on disjoint ranges of a shared resource each using atomic compare and swap (CAS) operations. A linked list of currently locked ranges is maintained and, upon entry to a lock acquisition operation, a thread waits for all locked ranges overlapping the desired range to be released then inserts a descriptor for the desired range into the linked list using a single CAS operation. To release a locked range, a thread executes a single fetch and add (FAA) operation. The operation may be extended to support simultaneous exclusive and non-exclusive access by allowing overlapping ranges to be locked for non-exclusive access and by performing an additional validation after locking to provide conflict resolution should a conflict be detected.

公开(公告)号：US20240265945A1

公开(公告)日：2024-08-08

申请号：US18617546

申请日：2024-03-26

Applicant: Oracle International Corporation

Inventor： David Dice ,  Alex Kogan

IPC: G11B20/10 ,  G06F9/52 ,  G06F16/23 ,  G11C16/26

CPC classification number: G11B20/10268 ,  G06F9/526 ,  G06F16/2343 ,  G06F16/2365 ,  G11B20/105 ,  G11C16/26

Abstract: A data object has a lock and a condition indicator associated with it. Based at least partly on detecting a first setting of the condition indicator, a reader stores an indication that the reader has obtained read access to the data object in an element of a readers structure and reads the data object without acquiring the lock. A writer detects the first setting and replaces it with a second setting, indicating that the lock is to be acquired by readers before reading the data object. Prior to performing a write on the data object, the writer verifies that one or more elements of the readers structure have been cleared.