公开(公告)号：US07936209B2

公开(公告)日：2011-05-03

申请号：US12428556

申请日：2009-04-23

Applicant: Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

Inventor： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H03K17/0822 ,  H03K19/018528

Abstract: Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

Abstract translation: 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

公开(公告)号：US20100332756A1

公开(公告)日：2010-12-30

申请号：US12495676

申请日：2009-06-30

Applicant: Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

Inventor： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

IPC: G06F12/08 ,  G06F1/30

CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F2201/82

Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from the write operations to memory. A register may be used to track the state of the cache and cause acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Other embodiments are also disclosed.

Abstract translation: 描述与处理镜像子系统的乱序事务相关的方法和装置。 在一个实施例中，在将写入操作的数据写入存储器之前，设备（即来自另一个设备的数据镜像）包括高速缓存以跟踪不合格的写入操作。 一旦由寄存器在选择点记录的所有高速缓存条目被清空或以其它方式被无效，则可以使用寄存器来跟踪高速缓存的状态并导致将数据承诺的确认。 还公开了其他实施例。

公开(公告)号：US07834653B1

公开(公告)日：2010-11-16

申请号：US12610275

申请日：2009-10-31

Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande

Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande

IPC: H03K19/007

CPC classification number: H03K19/00315 ,  H03K17/08104 ,  H03K19/007

Abstract: A method includes controllably utilizing a control signal generated by an Input/Output (IO) core to isolate a current path from an external voltage supplied through an IO pad to a supply voltage by transmitting a same voltage at an input terminal of a transistor, configured to be part of a number of cascaded transistors of an IO driver of an interface circuit, to an output terminal thereof during a failsafe mode of operation and a tolerant mode of operation. The method also includes feeding back an appropriate voltage to a floating node created by the isolation of the current path, and controlling a voltage across each transistor of the number of cascaded transistors to be within an upper tolerable limit thereof through an application of a gate voltage to each transistor derived from the supply voltage or the external voltage supplied through the IO pad.

Abstract translation: 一种方法包括可控地利用由输入/输出（IO）芯产生的控制信号，以将电流路径与通过IO垫提供的外部电压隔离成电源电压，通过在晶体管的输入端发送相同的电压，配置 作为接口电路的IO驱动器的多个级联晶体管的一部分，在故障安全操作模式和容限操作模式期间连接到其输出端子。 该方法还包括将适当的电压反馈到通过隔离电流路径而产生的浮动节点，并且通过施加栅极电压来控制级联晶体管数量的每个晶体管上的电压在其可容许的上限范围内 到源于通过IO焊盘提供的电源电压或外部电压的每个晶体管。

公开(公告)号：US07605642B2

公开(公告)日：2009-10-20

申请号：US11951381

申请日：2007-12-06

Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar

Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar

IPC: G05F1/10

CPC classification number: G05F3/08 ,  G05F3/30

Abstract: Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source.

Abstract translation: 电路和系统包括耦合到参考源的启动电路，用于向参考源提供启动电流，其中启动电路的晶体管不经受应力状况，并且其中启动电路在参考的稳定的稳态操作之后不消耗静态电流 资源。

公开(公告)号：US20090146728A1

公开(公告)日：2009-06-11

申请号：US11951381

申请日：2007-12-06

Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar

Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar

IPC: G05F1/10

CPC classification number: G05F3/08 ,  G05F3/30

Abstract: Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source.

Abstract translation: 电路和系统包括耦合到参考源的启动电路，用于向参考源提供启动电流，其中启动电路的晶体管不经受应力状况，并且其中启动电路在参考的稳定的稳态操作之后不消耗静态电流 资源。