公开(公告)号：US07936209B2

公开(公告)日：2011-05-03

申请号：US12428556

申请日：2009-04-23

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K17/0822 ,  H03K19/018528

摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

摘要翻译： 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

公开(公告)号：US20050134364A1

公开(公告)日：2005-06-23

申请号：US10744801

申请日：2003-12-23

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Bernard Morris ,  Jeffrey Nagy ,  Stefan Siegel

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Bernard Morris ,  Jeffrey Nagy ,  Stefan Siegel

IPC分类号： G05F3/02 ,  G05F3/24

CPC分类号： G05F3/245 ,  G05F3/247

摘要： A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.

摘要翻译： 补偿电路包括参考电路，该参考电路包括参考NMOS器件和参考PMOS器件。 参考电路可操作以产生第一参考信号和第二参考信号，第一参考信号是参考NMOS器件的处理特性，电压特性和温度特性中的至少一个的函数，第二参考信号 信号是参考PMOS器件的工艺特性，电压特性和温度特性中的至少一个的函数。 补偿电路还包括连接到参考电路的控制电路。 控制电路可操作以接收第一和第二参考信号并产生一个或多个输出信号，用于补偿至少一个NMOS器件的工艺特性，电压特性和温度特性中的至少一个的变化，并且在 响应于第一和第二参考信号，要补偿的电路中的至少一个PMOS器件可连接到控制电路。

公开(公告)号：US20100271118A1

公开(公告)日：2010-10-28

申请号：US12428556

申请日：2009-04-23

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

IPC分类号： G05F1/10

CPC分类号： H03K17/0822 ,  H03K19/018528

摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

摘要翻译： 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。