公开(公告)号：US20120166909A1

公开(公告)日：2012-06-28

申请号：US12976247

申请日：2010-12-22

Applicant: Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

Inventor： Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

IPC: G11C29/00

CPC classification number: G06F11/1076

Abstract: A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.

Abstract translation: 提供了一种方法和装置，用于在数据块从易失性存储器传输到非易失性存储装置的同时使数据块的数据完整性检查得以实现。 数据完整性检查与直接内存访问操作和独立磁盘冗余阵列（RAID）操作一起执行。 此外，在向RAID系统的存储设备传输期间以及在RAID更新和RAID数据重建操作期间执行RAID中的校验块的数据完整性检查。

公开(公告)号：US08125267B2

公开(公告)日：2012-02-28

申请号：US12889440

申请日：2010-09-24

Applicant: Pankaj Kumar ,  Pramod E Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

Inventor： Pankaj Kumar ,  Pramod E Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

IPC: G05F1/10

CPC classification number: H03K19/00315

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.

Abstract translation: 一种方法包括可控制地从电源电压产生第一偏置电压，使其处于集成电路的输入/输出（IO）核心器件的一个或多个构成的有源电路元件的工作电压的上容许限度内（ IC）与IO焊盘接口，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压，使其在所述一个或多个构成的有源电路元件的工作电压的上容许限度内 要与IO接口连接的IO内核设备。 该方法还包括可控制地利用由IO核心产生的控制信号，以在驱动器操作模式期间从第一偏置电压导出输出偏置电压，或者在故障安全操作模式和容限操作模式期间导出第二偏置电压。

公开(公告)号：US20110131373A1

公开(公告)日：2011-06-02

申请号：US12627440

申请日：2009-11-30

Applicant: Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

Inventor： Pankaj Kumar ,  Hang T. Nguyen ,  Mark Yarch ,  Timothy J. Jehl ,  John A. Miller

IPC: G06F12/08 ,  G06F12/00 ,  G06F12/16

CPC classification number: G06F11/2089 ,  G06F11/2097

Abstract: In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括用于控制包括多个盘的存储系统中的数据存储的罐。 多个罐中的每一个可以具有配置成用于单处理器模式并具有内部节点标识符以识别处理器和外部节点标识符的处理器，以识别用于镜像缓存数据的另一个处理器。 缓存数据的镜像可以通过经由PtP互连的非相干事务的通信来执行，其中PtP互连是根据高速缓存一致性协议。 描述和要求保护其他实施例。

公开(公告)号：US07936209B2

公开(公告)日：2011-05-03

申请号：US12428556

申请日：2009-04-23

Applicant: Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

Inventor： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H03K17/0822 ,  H03K19/018528

Abstract: Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

Abstract translation: 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

公开(公告)号：US20100332756A1

公开(公告)日：2010-12-30

申请号：US12495676

申请日：2009-06-30

Applicant: Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

Inventor： Mark A. Yarch ,  Pankaj Kumar ,  Hang T. Nguyen

IPC: G06F12/08 ,  G06F1/30

CPC classification number: G06F11/1666 ,  G06F11/20 ,  G06F2201/82

Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from the write operations to memory. A register may be used to track the state of the cache and cause acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Other embodiments are also disclosed.

Abstract translation: 描述与处理镜像子系统的乱序事务相关的方法和装置。 在一个实施例中，在将写入操作的数据写入存储器之前，设备（即来自另一个设备的数据镜像）包括高速缓存以跟踪不合格的写入操作。 一旦由寄存器在选择点记录的所有高速缓存条目被清空或以其它方式被无效，则可以使用寄存器来跟踪高速缓存的状态并导致将数据承诺的确认。 还公开了其他实施例。