公开(公告)号：US08929153B1

公开(公告)日：2015-01-06

申请号：US13975254

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Rakesh Kumar Sinha ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C7/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.

Abstract translation: 公开了具有多重读取字线设计的存储器的各种装置和方法。 存储器可以包括排列成行的多个比特单元，连接到多个比特单元的第一子集的第一读取字线和连接到多个比特单元的第二子集的第二读取字线，其中 第一和第二子集位于同一行位单元格中。 一种方法可以包括在第一读取操作期间断言连接到排列在位单元行中的多个位单元的第一子集的第一读取字线，并且在第二读取操作期间断言第二读取字线 连接到所述多个位单元的第二子集，其中所述第一和第二子集位于同一行比特单元中。

公开(公告)号：US08830779B1

公开(公告)日：2014-09-09

申请号：US13924916

申请日：2013-06-24

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

IPC: G11C17/18 ,  G11C7/06

CPC classification number: G11C5/14 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C17/16 ,  G11C17/18

Abstract: A fuse-based memory includes a plurality of bit lines. Each bit lines couples to a corresponding plurality of fuses. The fuses couple to ground through corresponding access transistors. The memory is configured to precharge an accessed one of the bit lines and a reference one of the bit lines using a low voltage supply. In contrast, a resulting voltage difference between the accessed bit line and the reference bit line is sensed using a sense amplifier powered by a high voltage supply, wherein a high voltage supplied by the high power supply is greater than a low voltage supplied by the low voltage supply.

Abstract translation: 基于熔丝的存储器包括多个位线。 每个位线耦合到相应的多个保险丝。 保险丝通过相应的存取晶体管耦合到地。 存储器被配置为使用低电压电源对所访问的位线之一和位线中的参考一个进行预充电。 相比之下，使用由高压电源供电的读出放大器来感测访问的位线和参考位线之间产生的电压差，其中由高电源提供的高电压大于由低电压提供的低电压 电压供应

公开(公告)号：US20140226418A1

公开(公告)日：2014-08-14

申请号：US13765533

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： Balachander Ganesan ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C7/00

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C7/18

Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p- channel metal-oxide-silicon (PMOS) transistor.

Abstract translation: 提供一种存储器电路，其包括耦合到位线的多个位单元，其允许访问来自多个位单元中的每一个的信息。 感测反相器耦合到位线的输出端。 保持器电路具有耦合到位线的输出以补偿来自多个位单元的电流泄漏。 保持器电路可以包括与p沟道金属氧化物 - 硅（PMOS）晶体管串联的n沟道金属氧化物 - 硅（NMOS）晶体管。