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    N-well switching circuit
    1.
    发明授权
    N-well switching circuit 有权
    N阱切换电路

    公开(公告)号：US08787096B1

    公开(公告)日：2014-07-22

    申请号：US13742964

    申请日：2013-01-16

    Applicant: QUALCOMM Incorporated

    Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

    IPC: G11C7/00 ,  G11C13/00

    CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

    Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

    Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。

    Global reset with replica for pulse latch pre-decoders
    2.
    发明授权
    Global reset with replica for pulse latch pre-decoders 有权
    脉冲锁存预解码器的全局复位

    公开(公告)号：US09036446B2

    公开(公告)日：2015-05-19

    申请号：US13663042

    申请日：2012-10-29

    Applicant: QUALCOMM Incorporated

    Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar ,  Balachander Ganesan ,  Alex Dongkyu Park

    IPC: G11C8/00 ,  G11C8/10

    CPC classification number: G11C8/10

    Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

    Abstract translation: 一种用于存储器中基于脉冲锁存器的预解码器的全局复位产生方法，包括产生用于脉冲锁存电路的预解码存储器地址输出，产生复位信号以复位脉冲锁存电路，提供预处理器的组合信号， 解码的存储器地址输出和复位信号，将组合的信号馈送到低电压阈值器件以操纵复位脉冲锁存电路，其中产生复位信号包括产生来自匹配电路的复位信号，该匹配电路被配置为模拟 锁存电路被复位并且其中产生复位信号包括配置匹配电路以适应最坏情况保持脉冲延迟，以允许在新的时钟周期执行复位之前复位脉冲锁存器并使匹配电路提供复位信号和 在同一电压域内预编译的存储器地址输出。

    Low voltage fuse-based memory with high voltage sense amplifier
    3.
    发明授权
    Low voltage fuse-based memory with high voltage sense amplifier 有权
    具有高电压读出放大器的低压熔丝式存储器

    公开(公告)号：US08830779B1

    公开(公告)日：2014-09-09

    申请号：US13924916

    申请日：2013-06-24

    Applicant: QUALCOMM Incorporated

    Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

    IPC: G11C17/18 ,  G11C7/06

    CPC classification number: G11C5/14 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C17/16 ,  G11C17/18

    Abstract: A fuse-based memory includes a plurality of bit lines. Each bit lines couples to a corresponding plurality of fuses. The fuses couple to ground through corresponding access transistors. The memory is configured to precharge an accessed one of the bit lines and a reference one of the bit lines using a low voltage supply. In contrast, a resulting voltage difference between the accessed bit line and the reference bit line is sensed using a sense amplifier powered by a high voltage supply, wherein a high voltage supplied by the high power supply is greater than a low voltage supplied by the low voltage supply.

    Abstract translation: 基于熔丝的存储器包括多个位线。 每个位线耦合到相应的多个保险丝。 保险丝通过相应的存取晶体管耦合到地。 存储器被配置为使用低电压电源对所访问的位线之一和位线中的参考一个进行预充电。 相比之下，使用由高压电源供电的读出放大器来感测访问的位线和参考位线之间产生的电压差，其中由高电源提供的高电压大于由低电压提供的低电压 电压供应

    WEAK KEEPER CIRCUIT FOR MEMORY DEVICE
    4.
    发明申请
    WEAK KEEPER CIRCUIT FOR MEMORY DEVICE 有权
    用于存储器件的弱保护电路

    公开(公告)号：US20140226418A1

    公开(公告)日：2014-08-14

    申请号：US13765533

    申请日：2013-02-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： Balachander Ganesan ,  Ritu Chaba ,  Sei Seung Yoon

    IPC: G11C7/00

    CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C7/18

    Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p- channel metal-oxide-silicon (PMOS) transistor.

    Abstract translation: 提供一种存储器电路，其包括耦合到位线的多个位单元，其允许访问来自多个位单元中的每一个的信息。 感测反相器耦合到位线的输出端。 保持器电路具有耦合到位线的输出以补偿来自多个位单元的电流泄漏。 保持器电路可以包括与p沟道金属氧化物 - 硅（PMOS）晶体管串联的n沟道金属氧化物 - 硅（NMOS）晶体管。

    Weak keeper circuit for memory device
    6.
    发明授权
    Weak keeper circuit for memory device 有权
    存储器件弱保护电路

    公开(公告)号：US09082465B2

    公开(公告)日：2015-07-14

    申请号：US13765533

    申请日：2013-02-12

    Applicant: QUALCOMM Incorporated

    Inventor： Balachander Ganesan ,  Ritu Chaba ,  Sei Seung Yoon

    IPC: G11C7/00 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18

    CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C7/18

    Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide-silicon (PMOS) transistor.

    Abstract translation: 提供一种存储器电路，其包括耦合到位线的多个位单元，其允许访问来自多个位单元中的每一个的信息。 感测反相器耦合到位线的输出端。 保持器电路具有耦合到位线的输出以补偿来自多个位单元的电流泄漏。 保持器电路可以包括与p沟道金属氧化物 - 硅（PMOS）晶体管串联的n沟道金属氧化物 - 硅（NMOS）晶体管。

    N-WELL SWITCHING CIRCUIT
    7.
    发明申请
    N-WELL SWITCHING CIRCUIT 有权
    N-Well切换电路

    公开(公告)号：US20140369152A1

    公开(公告)日：2014-12-18

    申请号：US14472953

    申请日：2014-08-29

    Applicant: QUALCOMM Incorporated

    Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

    IPC: H03K17/22 ,  H03K17/687 ,  G11C8/08

    CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

    Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

    Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。

    GLOBAL RESET WITH REPLICA FOR PULSE LATCH PRE-DECODERS
    9.
    发明申请
    GLOBAL RESET WITH REPLICA FOR PULSE LATCH PRE-DECODERS 有权
    全面复位与脉冲锁定前缀解码器

    公开(公告)号：US20130223178A1

    公开(公告)日：2013-08-29

    申请号：US13663042

    申请日：2012-10-29

    Applicant: QUALCOMM Incorporated

    Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar ,  Balachander Ganesan ,  Alex Dongkyu Park

    IPC: G11C8/10

    CPC classification number: G11C8/10

    Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

    Abstract translation: 一种用于存储器中基于脉冲锁存器的预解码器的全局复位产生方法，包括产生用于脉冲锁存电路的预解码存储器地址输出，产生复位信号以复位脉冲锁存电路，提供预处理器的组合信号， 解码的存储器地址输出和复位信号，将组合的信号馈送到低电压阈值器件以操纵复位脉冲锁存电路，其中产生复位信号包括产生来自匹配电路的复位信号，该匹配电路被配置为模拟 锁存电路被复位并且其中产生复位信号包括配置匹配电路以适应最坏情况保持脉冲延迟，以允许在新的时钟周期执行复位之前复位脉冲锁存器并使匹配电路提供复位信号和 在同一电压域内预编译的存储器地址输出。

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