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公开(公告)号：US11928020B2
公开(公告)日：2024-03-12
申请号：US18095341
申请日：2023-01-10
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Craig E. Hampel
CPC classification number: G06F11/1004 , G06F11/0703 , G06F11/073 , G06F11/1679 , H03M13/09
Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
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公开(公告)号：US11899571B2
公开(公告)日：2024-02-13
申请号：US17673277
申请日：2022-02-16
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Craig E. Hampel
IPC: G06F12/02
CPC classification number: G06F12/02 , G06F12/0292
Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.
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公开(公告)号：US20230388028A1
公开(公告)日：2023-11-30
申请号：US18138087
申请日：2023-04-23
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
CPC classification number: H04B17/11 , H04L7/0004 , H04L7/043 , H04L7/10 , H04L27/00 , H04B17/21 , H04L7/0016 , H04L7/0087 , H04B17/00
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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公开(公告)号：US20230224101A1
公开(公告)日：2023-07-13
申请号：US18078936
申请日：2022-12-10
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC: H04L1/24 , H04L7/00 , G11C7/10 , H04L25/02 , G11C29/02 , H04L25/12 , H04L27/00 , H04L7/10 , G11C7/04 , H04L7/033
CPC classification number: H04L1/242 , H04L7/0016 , G11C7/1084 , H04L25/0292 , G11C29/028 , H04L25/12 , G11C29/022 , H04L27/00 , G11C7/1057 , H04L7/10 , H04L7/0091 , G11C29/025 , H04L7/0087 , G11C7/04 , G11C2207/2254 , H04L7/033
Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
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公开(公告)号：US11552748B2
公开(公告)日：2023-01-10
申请号：US17386111
申请日：2021-07-27
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC: H04L7/00 , H04L1/24 , H04L7/10 , H04L25/02 , H04L25/12 , G11C29/02 , G11C7/10 , H04L27/00 , G11C7/04 , H04L7/033
Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
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Patent Agency Ranking
公开(公告)号：US11526632B2
公开(公告)日：2022-12-13
申请号：US16997661
申请日：2020-08-19
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Liji Gopalakrishnan , John Eric Linstadt , Steven C. Woo
Abstract: Methods and systems for enabling secure memory transactions in a memory controller are disclosed. Responsive to determining that an incoming request is for a secure memory transaction, the incoming request is placed in a secure request container. The memory container then enters a state where re-ordering between requests for secure memory transactions placed in the secure request container and requests for non-secure memory transactions from other containers is prevented in a scheduling queue.
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公开(公告)号：US20220276956A1
公开(公告)日：2022-09-01
申请号：US17673277
申请日：2022-02-16
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Craig E. Hampel
IPC: G06F12/02
Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.
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公开(公告)号：US20220069975A1
公开(公告)日：2022-03-03
申请号：US17409594
申请日：2021-08-23
Applicant: Rambus Inc.
Inventor： Bret G. Stott , Craig E. Hampel , Frederick A. Ware
Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
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公开(公告)号：US11256613B2
公开(公告)日：2022-02-22
申请号：US16214558
申请日：2018-12-10
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Craig E. Hampel
Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.
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公开(公告)号：US11115179B2
公开(公告)日：2021-09-07
申请号：US17000182
申请日：2020-08-21
Applicant: Rambus Inc.
Inventor： Bret G. Stott , Craig E. Hampel , Frederick A. Ware
Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
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