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公开(公告)号：US07779292B2
公开(公告)日：2010-08-17
申请号：US11836908
申请日：2007-08-10
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。
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62.发明授权Data processing system and method of communication that employ a request-and-forget protocol 失效采用请求忘记协议的数据处理系统和通信方法公开(公告)号：US06970936B2
公开(公告)日：2005-11-29
申请号：US09740220
申请日：2000-12-19
CPC分类号： G06F13/1642 , G06F12/0811 , G06F12/0815
摘要： A data processing system includes a requester having a request queue and a recipient. The requester, which buffers a request in an entry of the request queue, transmits the request to the recipient for servicing. According to the request-and-forget protocol, the requester removes the request from the entry of the request queue without receipt of any indication that the request has been serviced.
摘要翻译： 数据处理系统包括具有请求队列和接收者的请求者。 在请求队列的条目中缓存请求的请求者将请求发送给接收方进行维修。 根据请求忘记协议，请求者从请求队列的条目中移除请求，而不接收到任何指示已经被服务的指示。
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63.发明授权Data processing system and method for efficient storage of metadata in a system memory 失效用于在系统存储器中有效存储元数据的数据处理系统和方法公开(公告)号：US07467323B2
公开(公告)日：2008-12-16
申请号：US11055640
申请日：2005-02-10
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。
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64.发明授权Data processing system and method for efficient coherency communication utilizing coherency domain indicators 有权数据处理系统和方法，利用相干域指标进行有效的一致性通信公开(公告)号：US07774555B2
公开(公告)日：2010-08-10
申请号：US11835259
申请日：2007-08-07
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译： 在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内 域。 第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播 系统按照确定。
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65.发明授权公开(公告)号：US06493814B2
公开(公告)日：2002-12-10
申请号：US09801610
申请日：2001-03-08
IPC分类号： G06F1200
CPC分类号： G06F12/0811
摘要： A system and method for reducing resource collisions associated with memory units. Resource collisions may be reduced in part by a hash that combines the number N bits in the bank selector field with the number M bits adjacent to a region of correlation, e.g., row selector field, in an address to determine which bank in a memory unit, e.g., cache, may store the information associated with the address.
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66.发明授权Data processing system and method for efficient coherency communication utilizing coherency domains 失效数据处理系统和方法，利用一致性域进行有效的一致性通信公开(公告)号：US08214600B2
公开(公告)日：2012-07-03
申请号：US11055402
申请日：2005-02-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0831
摘要： In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency domain. The master receives a response of the first coherency domain to the first broadcast of the operation. If the response indicates the operation cannot be serviced in the first coherency domain alone, the master increases the scope of transmission by performing a second broadcast of the operation in both the first and second coherency domains. If the response indicates the operation can be serviced in the first coherency domain, the master refrains from performing the second broadcast.
摘要翻译： 在包括至少第一和第二相干域的高速缓存相干数据处理系统中，主器件在高速缓存相干数据处理系统内进行第一广播，其被限制在传输范围到第一相干域。 主机接收第一个一致性域的响应到该操作的第一次广播。 如果响应指示仅在第一个相干域中不能进行操作，则主设备通过在第一和第二相干域中执行操作的第二次广播来增加传输的范围。 如果响应指示可以在第一相干域中服务操作，则主机不执行第二广播。
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67.发明授权公开(公告)号：US07454577B2
公开(公告)日：2008-11-18
申请号：US11055476
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Benjiman Lee Goodman , Guy Lynn Guthrie , William John Starke , Derek Edward Williams
发明人： James Stephen Fields, Jr. , Benjiman Lee Goodman , Guy Lynn Guthrie , William John Starke , Derek Edward Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F12/084
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.
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68.发明授权公开(公告)号：US08001330B2
公开(公告)日：2011-08-16
申请号：US12325266
申请日：2008-12-01
IPC分类号： G06F13/00
CPC分类号： G06F12/0851 , G06F12/0811
摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.
摘要翻译： 缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分区成至少两个切片，并且使用第一目录来访问第一阵列片，同时使用第二目录来访问第二阵列片，但是从高速缓存目录 使用控制单个访问/命令端口的单个缓存仲裁器进行管理。 在一个实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与高速缓存仲裁器通信。 高速缓存阵列布置有高速缓存扇区的行和列，其中高速缓存行分布在不同行和列中的扇区之间，其中一部分给定高速缓存行位于具有第一延迟的第一列中，并且给定的另一部分 高速缓存线位于具有大于第一等待时间的第二等待时间的第二列中。
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公开(公告)号：US07827354B2
公开(公告)日：2010-11-02
申请号：US11923952
申请日：2007-10-25
申请人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , Bradley David McCredie , William John Starke
发明人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , Bradley David McCredie , William John Starke
CPC分类号： G06F12/0897 , G06F12/127
摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.
摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。 在替代实施例中，利用直接干预来访问相同级别的受害者缓存。
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公开(公告)号：US07783841B2
公开(公告)日：2010-08-24
申请号：US11836965
申请日：2007-08-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。 高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。
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