公开(公告)号：US20140115207A1

公开(公告)日：2014-04-24

申请号：US13976937

申请日：2013-03-27

申请人： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra Das Sharma ,  Jeffrey C. Swanson

发明人： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra Das Sharma ,  Jeffrey C. Swanson

IPC分类号： G06F13/42

CPC分类号： G06F13/4291 ,  G06F1/24 ,  G06F1/3287 ,  G06F13/1678 ,  G06F13/42 ,  G06F13/4282 ,  G06N99/005

摘要： A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

摘要翻译： 周期性控制窗口嵌入在要通过串行数据链路发送的链路层数据流中，其中控制窗口被配置为提供物理层信息，包括用于启动数据链路上的状态转换的信息。 可以在数据链路的链路发送状态期间发送链路层数据，并且控制窗口可以中断发送猝发。 在一个方面，信息包括指示改变链路上的活动车道数目的尝试的链路宽度转换数据。

公开(公告)号：US20130132683A1

公开(公告)日：2013-05-23

申请号：US13713614

申请日：2012-12-13

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US08209563B2

公开(公告)日：2012-06-26

申请号：US12756998

申请日：2010-04-08

申请人： Debendra Das Sharma ,  Gurushankar Rajamani ,  Hanh Hoang

发明人： Debendra Das Sharma ,  Gurushankar Rajamani ,  Hanh Hoang

IPC分类号： G06F1/04 ,  G06F17/50 ,  G06G7/62

CPC分类号： H04L49/9078 ,  H04L49/90

摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。

公开(公告)号：US08099523B2

公开(公告)日：2012-01-17

申请号：US13073219

申请日：2011-03-28

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20110238882A1

公开(公告)日：2011-09-29

申请号：US13073149

申请日：2011-03-28

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/14

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US07958404B2

公开(公告)日：2011-06-07

申请号：US12414733

申请日：2009-03-31

申请人： Keith Drescher ,  Debendra Das Sharma ,  David Sams ,  Richard Glass

发明人： Keith Drescher ,  Debendra Das Sharma ,  David Sams ,  Richard Glass

IPC分类号： G06F11/00

CPC分类号： G01R31/3177

摘要： In one embodiment, a state machine may enable retraining of a link, where the state machine is to be initiated responsive to an external input received from a logic analyzer coupled to the link or a periodic timer. Such external input may indicate that the logic analyzer has lost synchronization with respect to link communications, and the retraining thus enables the logic analyzer to regain resynchronization. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，状态机可以允许重新训练链路，其中响应于从耦合到链路的逻辑分析器接收的外部输入或周期性定时器来启动状态机。 这种外部输入可以指示逻辑分析仪相对于链路通信已经失去同步，并且再训练使得逻辑分析仪能够重新获得重新同步。 描述和要求保护其他实施例。

公开(公告)号：US20110072164A1

公开(公告)日：2011-03-24

申请号：US12883781

申请日：2010-09-16

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F13/42

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US07899111B2

公开(公告)日：2011-03-01

申请号：US11835380

申请日：2007-08-07

申请人： Debendra Das Sharma ,  David J. Harriman

发明人： Debendra Das Sharma ,  David J. Harriman

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： H04L25/4908 ,  H04L25/0272

摘要： In some embodiments, a chip includes transmitters and generation circuitry to provide data symbols and special characters to the transmitters to be transmitted. The chip also includes match detection circuitry to detect when the data symbols match the special characters; and indicator symbol generation circuitry to create data indicator symbols in response to detected matches and to provide the data indicator symbols to the generation circuitry to be provided to the transmitters to be transmitted. Other embodiments are described.

摘要翻译： 在一些实施例中，芯片包括发送器和产生电路，以向要发送的发送器提供数据符号和特殊字符。 芯片还包括匹配检测电路，用于检测数据符号与特殊字符匹配的时间; 以及指示符符号生成电路，用于响应于检测到的匹配而创建数据指示符符号，并将数据指示符符号提供给要提供给要发送的发送器的生成电路。 描述其他实施例。

公开(公告)号：US20100329255A1

公开(公告)日：2010-12-30

申请号：US12492304

申请日：2009-06-26

申请人： Abhishek Singhal ,  Debendra Das Sharma ,  Jesus Palomino ,  Mario A. Rubio

发明人： Abhishek Singhal ,  Debendra Das Sharma ,  Jesus Palomino ,  Mario A. Rubio

IPC分类号： H04L12/56

CPC分类号： H04L69/04 ,  H04L49/9042 ,  H04L49/9094

摘要： In one embodiment, the present invention includes a method for comparing a packet header to a stored packet header, generating a comparison vector based on the comparison, and transmitting the packet from the transmitter without the packet header if the packet header and the stored packet header match. A data portion of the packet may be compressed and transmitted using a different compression technique. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于将分组报头与存储的分组报头进行比较的方法，基于比较生成比较向量，并且如果分组报头和存储的分组报头，则从发送器发送分组而不使用分组报头 比赛。 可以使用不同的压缩技术来压缩和发送分组的数据部分。 描述和要求保护其他实施例。

公开(公告)号：US07757020B2

公开(公告)日：2010-07-13

申请号：US11169527

申请日：2005-06-29

申请人： Debendra Das Sharma ,  Ajay V. Bhatt

发明人： Debendra Das Sharma ,  Ajay V. Bhatt

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4278 ,  Y02D10/14 ,  Y02D10/151

摘要： Point-to-point links between devices are brought up at a slowest available speed, and a faster link speed is negotiated after reaching an operational state.

摘要翻译： 设备之间的点对点链路以最慢的可用速度启动，并且在达到操作状态之后协商更快的链路速度。