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公开(公告)号：US20100329255A1
公开(公告)日：2010-12-30
申请号：US12492304
申请日：2009-06-26
IPC分类号： H04L12/56
CPC分类号： H04L69/04 , H04L49/9042 , H04L49/9094
摘要： In one embodiment, the present invention includes a method for comparing a packet header to a stored packet header, generating a comparison vector based on the comparison, and transmitting the packet from the transmitter without the packet header if the packet header and the stored packet header match. A data portion of the packet may be compressed and transmitted using a different compression technique. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于将分组报头与存储的分组报头进行比较的方法，基于比较生成比较向量，并且如果分组报头和存储的分组报头，则从发送器发送分组而不使用分组报头 比赛。 可以使用不同的压缩技术来压缩和发送分组的数据部分。 描述和要求保护其他实施例。
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公开(公告)号：US08111704B2
公开(公告)日：2012-02-07
申请号：US12492304
申请日：2009-06-26
CPC分类号： H04L69/04 , H04L49/9042 , H04L49/9094
摘要： In one embodiment, the present invention includes a method for comparing a packet header to a stored packet header, generating a comparison vector based on the comparison, and transmitting the packet from the transmitter without the packet header if the packet header and the stored packet header match. A data portion of the packet may be compressed and transmitted using a different compression technique. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于将分组报头与存储的分组报头进行比较的方法，基于比较生成比较向量，并且如果分组报头和存储的分组报头，则从发送器发送分组而不使用分组报头 比赛。 可以使用不同的压缩技术来压缩和发送分组的数据部分。 描述和要求保护其他实施例。
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公开(公告)号：US20220261308A1
公开(公告)日：2022-08-18
申请号：US17733627
申请日：2022-04-29
申请人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Swadesh Choudhary , Zuoguo Wu , Gerald Pasdast
发明人： Narasimha Lanka , Debendra Das Sharma , Lakshmipriya Seshan , Swadesh Choudhary , Zuoguo Wu , Gerald Pasdast
摘要： Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.
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公开(公告)号：US20220116138A1
公开(公告)日：2022-04-14
申请号：US17556685
申请日：2021-12-20
申请人： Debendra Das Sharma
发明人： Debendra Das Sharma
摘要： A first flit is generated according to a first flit format, where a first number of error detection codes are to be provided for an amount of data to be sent in the first flit, and the first flit is to be sent on a link by the transmitter while the link operates with a first link width. The link transitions from a first link width to a second link width, where the second link width is narrower than the first link width. A second flit is generated according to a second flit format based on the transition to the second link width, where the second flit is to be sent while the link operates at the second link width, and the second flit format defines that a second, higher number of error detection codes are to be provided for the same amount of data.
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5.发明申请公开(公告)号：US20210232520A1
公开(公告)日：2021-07-29
申请号：US17231152
申请日：2021-04-15
摘要： In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.
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6.发明授权公开(公告)号：US09645965B2
公开(公告)日：2017-05-09
申请号：US13840104
申请日：2013-03-15
申请人： Debendra Das Sharma , Kanaka Lakshimi Siva Prasad Gadey Naga Venkata , Prahladachar Jayaprakash Bharadwaj
发明人： Debendra Das Sharma , Kanaka Lakshimi Siva Prasad Gadey Naga Venkata , Prahladachar Jayaprakash Bharadwaj
CPC分类号： G06F13/4282 , H04L5/1438 , H04L25/0272 , H04L25/03019 , H04L25/03885 , H04L2025/03802 , H04L2025/03808 , Y02D10/14 , Y02D10/151
摘要： A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to communicate a first set of data to the link partner component. The first component may comprise at least one receiver to receive a first set of equalization data. The first component may further comprise coefficient storage coupled to the receiver to store the equalization data. In addition, coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data. The first component is to send the first set of coefficients to the link partner component.
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7.发明授权公开(公告)号：US09442879B2
公开(公告)日：2016-09-13
申请号：US13994128
申请日：2011-12-07
CPC分类号： G06F13/4282 , G06F12/0831 , G06F13/00 , G06F13/14 , G06F13/38 , G06F13/4234 , G06F13/426 , G06F15/781 , G06F2212/621 , G06F2213/0008 , G06F2213/0024 , G06F2213/0026 , H04L12/00
摘要： Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.
摘要翻译： 用于通过高速互连传输包括多条交易数据的数据单元的方法，装置和系统。 称为KTI（Keizer Technology Interface）的流量控制单元以支持相干存储器事务的相干多层协议实现。 KTI Flit具有一种基本格式，支持使用可配置字段来实现可用于相应事务的特定格式的KTI Flits。 在一个方面，KTI Flit可以被格式化为用于支持在单个Flit中传送多个相应交易数据的多个时隙。 KTI Flit也可以配置为支持各种类型的事务，并且可以将多个KTI Flits组合成数据包，以支持数据传输，如缓存线传输。
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公开(公告)号：US20150186069A1
公开(公告)日：2015-07-02
申请号：US14142697
申请日：2013-12-27
IPC分类号： G06F3/06
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/061 , G06F3/0631 , G06F3/067 , G06F3/0679 , G06F9/5016 , G06F2209/5011
摘要： An apparatus for pooling memory resources across multiple nodes is described herein. The apparatus includes a shared memory controller, wherein each node of the multiple nodes is connected to the shared memory controller. The apparatus also includes a pool of memory connected to the shared memory controller, wherein a portion of the pool of memory is allocated to each node of the multiple nodes.
摘要翻译： 本文描述了用于在多个节点之间汇集存储器资源的装置。 该装置包括共享存储器控制器，其中多个节点的每个节点连接到共享存储器控制器。 该装置还包括连接到共享存储器控制器的存储器池，其中存储器池的一部分被分配给多个节点的每个节点。
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9.发明申请METHOD, APPARATUS, SYSTEM FOR LANE STAGGERING AND DETERMINISM FOR SERIAL HIGH SPEED I/O LANES 有权方法，装置，用于串行高速I / O域的LANE分析和确定的系统公开(公告)号：US20150185809A1
公开(公告)日：2015-07-02
申请号：US14141184
申请日：2013-12-26
申请人： Prahladachar Jayaprakash Bharadwaj , Debendra Das Sharma , Harshit Poladia , Kanaka Lakshmi Gadey Naga Venkata
发明人： Prahladachar Jayaprakash Bharadwaj , Debendra Das Sharma , Harshit Poladia , Kanaka Lakshmi Gadey Naga Venkata
CPC分类号： G06F1/3253 , G06F1/3278 , G06F13/4027 , Y02D10/151 , Y02D10/157 , Y02D50/20
摘要： A method of staggering lanes in a peripheral component interconnect express (PCI-Express) port is described herein. The method includes initiating the port to enter or exit an electrical idle state. The method also includes forwarding a token to a predetermined lane of the port. Additionally, the method includes turning the predetermined lane ON or OFF by indication to an analog circuit interface. The method also includes forwarding the token to a neighboring lane when a staggering interval timer elapses.
摘要翻译： 本文描述了外围组件互连快速（PCI-Express）端口中的交错通道的方法。 该方法包括启动端口进入或退出电气空闲状态。 该方法还包括将令牌转发到端口的预定通道。 此外，该方法包括通过指示将预定通道打开或关闭到模拟电路接口。 该方法还包括当令牌间隔计时器经过时将令牌转发到相邻车道。
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10.发明申请公开(公告)号：US20140095751A1
公开(公告)日：2014-04-03
申请号：US13631876
申请日：2012-09-29
IPC分类号： G06F13/38
CPC分类号： G06F13/42 , G06F1/3253 , G06F13/38 , G06F13/382 , G06F13/4265 , Y02D10/14 , Y02D10/151
摘要： Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed.
摘要翻译： 描述了在退出低功率部分宽度高速链路状态时与快速偏移校正有关的方法和装置。 在一个实施例中，可以在第一时间点上传输有效车道上的出口飞行和/或空闲车道上的唤醒信号/序列，以使链路的一个或多个空闲车道进入活动状态。 在第二时间点（在第一时间点之后或之后），在链路的一个或多个空闲车道上发送训练序列。 并且，一个或多个空闲车道响应于训练序列而在第三时间点之前（在第二时间点之后或之后的其他时间）进行了偏斜校正。 还公开并要求保护其他实施例。
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