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    FREQUENCY CALIBRATION METHOD APPLICABLE IN UNIVERSAL SERIAL BUS DEVICE AND RELATED UNIVERSAL SERIAL BUS DEVICE
    2.
    发明申请
    FREQUENCY CALIBRATION METHOD APPLICABLE IN UNIVERSAL SERIAL BUS DEVICE AND RELATED UNIVERSAL SERIAL BUS DEVICE 审中-公开

    公开(公告)号：US20180136691A1

    公开(公告)日：2018-05-17

    申请号：US15871011

    申请日：2018-01-14

    申请人： Silicon Motion Inc.

    发明人： Liang-Hsuan Lu

    IPC分类号： G06F1/08 ,  G06F13/42 ,  G06F13/40

    CPC分类号： G06F1/08 ,  G06F13/4068 ,  G06F13/4278

    摘要： A frequency calibration method applied to a Universal Serial Bus (USB) device includes: coupling the USB device to a USB host, wherein the USB device comprises at least a programmable oscillator; utilizing the USB device to extract a low frequency periodic signal from the USB host; calibrating the programmable oscillator of the USB device according to the low frequency periodic signal, to make the programmable oscillator generate an oscillating signal having a predetermined frequency; and when the USB device receives the low frequency periodic signal from the USB host, controlling the USB device to generate a predetermined signal having a frequency higher than a frequency of the low frequency periodic signal to the USB host, to make the USB host continuously generate the low frequency periodic signal to the USB device.

    Self track scheme for multi frequency band serializer de-serializer I/O circuits
    3.
    发明授权
    Self track scheme for multi frequency band serializer de-serializer I/O circuits 有权
    多频段串行器解串行器I / O电路的自跟踪方案

    公开(公告)号：US09426016B2

    公开(公告)日：2016-08-23

    申请号：US14704694

    申请日：2015-05-05

    申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    发明人： Sheau Jiung Lee ,  Mau-Chung Frank Chang ,  Yanghyo Kim

    IPC分类号： H04M11/06 ,  H04L27/38 ,  G06F13/40 ,  G06F5/16 ,  H04L27/36

    CPC分类号： H04L27/38 ,  G06F5/16 ,  G06F13/4059 ,  G06F13/4072 ,  G06F13/4278 ,  H04L27/364

    摘要： A serializer and de-serializer circuit having self tracking circuitry which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency modulation mechanism (e.g., QAM) for converting digital data bits into a serial analog stream at multiple frequencies for communication over a chip I/O connection. The track pulse generated on the transmitter side is serialized through the same path as the data, and demodulated through the same path in the de-serializer to provide synchronization with the data, without the need for complicated base band processing.

    摘要翻译： 具有自我跟踪电路的串行器和解串器电路，其特别适用于将数字数据从一个集成电路（芯片）传送到另一个集成电路（芯片）到另一个用于实现芯片到芯片通信。 这些电路是可扩展的并且利用多频调制机制（例如，QAM），用于将数字数据位转换成多个频率的串行模拟流，用于通过芯片I / O连接进行通信。 在发射机侧产生的跟踪脉冲通过与数据相同的路径进行串行化，并通过解串器中相同的路径解调，以提供与数据的同步，而不需要复杂的基带处理。

    N-phase signal transition alignment
    5.
    发明授权
    N-phase signal transition alignment 有权
    N相信号转换对齐

    公开(公告)号：US09276731B2

    公开(公告)日：2016-03-01

    申请号：US14453346

    申请日：2014-08-06

    申请人： QUALCOMM Incorporated

    发明人： Chulkyu Lee ,  George Alan Wiley

    IPC分类号： H04L7/00 ,  G06F13/42 ,  H04L25/49

    CPC分类号： G06F13/36 ,  G06F13/4063 ,  G06F13/4068 ,  G06F13/4278 ,  G06F13/4282 ,  H04L7/0033 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/4919 ,  Y02D10/14 ,  Y02D10/151

    摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

    摘要翻译： 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 驱动器可以被适配或配置成在两个或更多个连接器上对准状态转换，以使连续符号之间的过渡周期最小化。 驱动器可以包括推进或延迟某些转换的电路。 驱动器可以包括预加重电路，即，即使当连接器转换到未驱动状态时，该预加重电路用于驱动连接器的一部分过渡期的状态。

    BUS INTERFACE SYSTEM
    6.
    发明申请
    BUS INTERFACE SYSTEM 审中-公开
    总线接口系统

    公开(公告)号：US20150169482A1

    公开(公告)日：2015-06-18

    申请号：US14575491

    申请日：2014-12-18

    申请人： RF MICRO DEVICES, INC.

    发明人： Christopher Truong Ngo ,  Alexander Wayne Hietala ,  Christian Rye Iversen ,  Ruediger Bauder

    IPC分类号： G06F13/362 ,  G06F1/08

    CPC分类号： G06F13/3625 ,  G06F13/4278 ,  Y02D10/14 ,  Y02D10/151

    摘要： A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

    摘要翻译： 公开了一种总线接口系统，其包括通过总线耦合的主总线控制器和从总线控制器。 从总线控制器包括允许数据沿着总线传输的解码器。 解码器包括振荡器，第一计数器和比较电路。 振荡器被配置为通过由输入数据信号定义的数据脉冲使能，并在使能时产生振荡脉冲。 第一个对振荡脉冲进行计数，并指示在时隙期间产生的振荡脉冲的数量。 比较电路被配置为具有参考号的该号码，并且响应于该数量大于参考参数而生成表示第一逻辑值的数据输出，并且响应于小于参考的数字表示第二逻辑值 参数。

    Multirate transmission system and method for parallel input data
    7.
    发明授权
    Multirate transmission system and method for parallel input data 有权
    多速率传输系统和并行输入数据的方法

    公开(公告)号：US08880928B2

    公开(公告)日：2014-11-04

    申请号：US12082685

    申请日：2008-04-11

    申请人： Mark Stephen Remlin ,  Michael George Engler

    发明人： Mark Stephen Remlin ,  Michael George Engler

    IPC分类号： G06F5/06 ,  G06F13/42 ,  G06F13/40

    CPC分类号： G06F13/4278 ,  G06F13/4045

    摘要： A multirate transmission system for transmitting parallel input data from a first location to a second location includes a transmitter portion and a receiver portion. The transmitter portion receives the parallel data, including the information related to a parallel data clock and stores the data in a buffer where it is subsequently read and serialized for transmission on a serial data link to the receiver portion where it is deserialized, including recovery of the parallel data clock in the serialized data stream. The receiver portion stores the parallel data in a buffer where it is read at a data rate corresponding to the parallel data clock of the incoming parallel data. The parallel data at the transmitter portion is associated with generated control characters when parallel data is not read from the buffer associated with the transmitter portion.

    摘要翻译： 用于将并行输入数据从第一位置传输到第二位置的多速率传输系统包括发射机部分和接收机部分。 发送器部分接收并行数据，包括与并行数据时钟有关的信息，并将数据存储在缓冲器中，随后读取和串行化数据，以便在串行数据链路上发送到被反序列化的接收器部分，包括恢复 串行数据流中的并行数据时钟。 接收器部分将并行数据存储在缓冲器中，在缓冲器中以与输入并行数据的并行数据时钟对应的数据速率读取数据。 当从与发送器部分相关联的缓冲器未读取并行数据时，发送器部分处的并行数据与所生成的控制字符相关联。

    Pseudo-synchronous time division multiplexing
    8.
    发明授权
    Pseudo-synchronous time division multiplexing 有权
    伪同步时分复用

    公开(公告)号：US08724665B2

    公开(公告)日：2014-05-13

    申请号：US12506200

    申请日：2009-07-20

    申请人： Kenneth S. McElvain

    发明人： Kenneth S. McElvain

    IPC分类号： H04J3/02

    CPC分类号： G06F17/5045 ,  G06F13/4278 ,  H04J3/047 ,  H04J3/0602

    摘要： Methods and apparatuses to multiplex logic data pseudo synchronously are described. A representation of a multiplexer logic is generated to transmit data items asynchronously relative to a design clock. The data items may be transmitted under control of a transmission clock from a first integrated circuit to a second integrated circuit. A representation of a counter logic may be generated to couple with the multiplexer logic for transmitting the data asynchronously. Additionally, a representation of reset logic may be generated for a configuration to repeatedly reset the counter logic. Synchronization signals may be generated for a design clock cycle of a design clock driving the data items. The synchronization signals may be transmitted via the transmission clock asynchronous with the design clock. The data items may be transmitted via a number of transmission slots determined based on the clock cycles of the transmission clock and the design clock The total time for the transmission slots for transmitting the logic data may be less than the clock cycle of the design clock. One or more transmission slots within the clock cycle of the design clock may be used to transmit the synchronization data to indicate a new cycle to transmit the data items according to the design clock.

    摘要翻译： 描述了伪同步复用逻辑数据的方法和装置。 生成多路复用器逻辑的表示以相对于设计时钟异步地发送数据项。 数据项可以在传输时钟的控制下从第一集成电路传输到第二集成电路。 可以产生计数器逻辑的表示以与用于异步发送数据的多路复用器逻辑耦合。 另外，可以为配置重复复位计数器逻辑而产生复位逻辑的表示。 可以为驱动数据项的设计时钟的设计时钟周期生成同步信号。 同步信号可以经由与设计时钟异步的传输时钟传输。 可以经由基于传输时钟和设计时钟的时钟周期确定的多个传输时隙来发送数据项。用于发送逻辑数据的传输时隙的总时间可以小于设计时钟的时钟周期。 设计时钟的时钟周期内的一个或多个传输时隙可用于发送同步数据以指示根据设计时钟发送数据项的新周期。

    Single General Purpose Input/Output (GPIO) Pin Motor Control Circuit
    9.
    发明申请
    Single General Purpose Input/Output (GPIO) Pin Motor Control Circuit 有权
    单通用输入/输出（GPIO）引脚电机控制电路

    公开(公告)号：US20110031905A1

    公开(公告)日：2011-02-10

    申请号：US12299241

    申请日：2008-06-12

    申请人： Gaile Lin ,  Guoquan Li ,  Hong Guan

    发明人： Gaile Lin ,  Guoquan Li ,  Hong Guan

    IPC分类号： H02P1/02 ,  H02K7/14

    CPC分类号： G06F13/4278 ,  G06F1/22

    摘要： System and method for operating a motor using a single general purpose input/output (GPIO) pin of a controller. In one embodiment, a control circuit may include a first terminal coupled to a GPIO pin of a controller. The first terminal can be configured to receive, and output, at least one or more signals. The control circuit may include a plurality of elements coupled to the first terminal, and motor driver circuit output terminal, such that the control circuit may be configured to output one more control signals to the motor driver circuit output terminal for control the motor driver circuit. Motor driver control signals may be based, at least in part, on one or more signals received from the first terminal.

    摘要翻译： 使用控制器的单个通用输入/输出（GPIO）引脚来操作电机的系统和方法。 在一个实施例中，控制电路可以包括耦合到控制器的GPIO引脚的第一端子。 第一终端可以被配置为接收和输出至少一个或多个信号。 控制电路可以包括耦合到第一端子的多个元件和电动机驱动器电路输出端子，使得控制电路可以被配置为将一个或多个控制信号输出到电动机驱动器电路输出端子，以控制电动机驱动器电路 。 至少部分地，电动机驱动器控制信号可以基于从第一终端接收的一个或多个信号。

    Providing an arrangement of memory devices to enable high-speed data access
    10.
    发明授权
    Providing an arrangement of memory devices to enable high-speed data access 有权
    提供存储器件的布置以实现高速数据访问

    公开(公告)号：US07020757B2

    公开(公告)日：2006-03-28

    申请号：US10400371

    申请日：2003-03-27

    申请人： Michael Ruhovets ,  Christopher C. Wanner

    发明人： Michael Ruhovets ,  Christopher C. Wanner

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4243 ,  G06F13/4278 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： A memory subsystem includes multiple memory modules coupled by point-to-point links. A memory controller is coupled by a point-to-point link to a first memory module, which is turn is coupled by another point-to-point link to another memory module. Further memory modules may be coupled by respective point-to-point links in the memory subsystem. In some arrangements, each memory module tracks commands issued to other memory modules, such as more upstream memory modules. Also, in one example implementation, a clock is embedded within a data stream transmitted over a point-to-point link, so that an external clock is not employed in this example implementation.

    摘要翻译： 存储器子系统包括通过点对点链接耦合的多个存储器模块。 存储器控制器通过点对点链路耦合到第一存储器模块，第一存储器模块通过另一个点到点链路耦合到另一个存储器模块。 另外的存储器模块可以通过存储器子系统中的相应点对点链路耦合。 在一些布置中，每个存储器模块跟踪发给其他存储器模块的命令，诸如更上游的存储器模块。 此外，在一个示例实现中，时钟被嵌入在通过点对点链路传输的数据流中，使得在该示例实现中不使用外部时钟。