公开(公告)号：US20250061833A1

公开(公告)日：2025-02-20

申请号：US18718315

申请日：2022-12-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Susumu KAWASHIMA ,  Koji KUSUNOKI ,  Tomoaki ATSUMI ,  Naoto KUSUMOTO

IPC: G09G3/20 ,  G09G3/32 ,  H01L25/16 ,  H01L27/12

Abstract: A display device whose change in chromaticity is small and grayscale controllability is high is provided. The display device can turn on and turn off a light-emitting device by PAM and PWM control (a pulse width control involving changes in amplitude). The display device writes the same input signal (data potential) to a first node and a second node to turn on the light-emitting device in accordance with a potential of the first node and generate a pulse signal in accordance with a potential of the second node. The potential of the first node can be reset in accordance with the generated pulse signal. Therefore, the light-emitting device can emit light for a desired period with a desired emission intensity.

公开(公告)号：US20240412687A1

公开(公告)日：2024-12-12

申请号：US18695921

申请日：2022-10-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji KUSUNOKI ,  Tomoaki ATSUMI ,  Hideaki SHISHIDO ,  Susumu KAWASHIMA

IPC: G09G3/3233 ,  G09G3/3266 ,  H10K59/127 ,  H10K59/131 ,  H10K59/35

Abstract: A display apparatus with a novel structure is provided. The display apparatus includes a display portion where a first transistor and a display element are provided to be stacked. The display portion includes a first sub-display portion and a second sub-display portion. The first sub-display portion and the second sub-display portion each include a plurality of pixel circuits each controlling the display element and a gate line driver circuit outputting a signal for driving the plurality of pixel circuits. The gate line driver circuit and the plurality of pixel circuits each include a first transistor. In the display portion, the number of image rewriting times per unit time for image data in the first sub-display portion is smaller than the number of image rewriting times per unit time for image data in the second sub-display portion.

公开(公告)号：US20240290261A1

公开(公告)日：2024-08-29

申请号：US18294395

申请日：2022-08-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Koji KUSUNOKI ,  Susumu KAWASHIMA ,  Tomoaki ATSUMI

IPC: G09G3/3233 ,  G09G3/00

CPC classification number: G09G3/3233 ,  G09G3/006 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0295 ,  G09G2320/045 ,  G09G2330/021

Abstract: A novel correction method of a display apparatus is provided. One embodiment of the present invention is a correction method of a display apparatus. The correction method includes processing in which a voltage correcting a threshold voltage of the transistor is obtained and the voltage is held in the capacitor; processing in which current flowing through the pixel is measured and a second signal based on the current is generated in the first circuit; processing in which the first signal correcting image data using the second signal is generated in the second circuit; and processing in which the first signal is supplied to the pixel.

公开(公告)号：US20240237376A9

公开(公告)日：2024-07-11

申请号：US18546685

申请日：2022-02-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Koji KUSUNOKI ,  Kazunori WATANABE ,  Tomoaki ATSUMI ,  Satoshi YOSHIMOTO

IPC: H10K39/34 ,  G06F3/042 ,  G06V40/13 ,  G09G3/3233 ,  H10K59/131

CPC classification number: H10K39/34 ,  G06F3/042 ,  G06V40/1318 ,  G09G3/3233 ,  H10K59/131 ,  G06F2203/04108 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2354/00 ,  G09G2360/14

Abstract: A semiconductor device having a light sensing function and including a high-resolution display portion is provided. The semiconductor device includes a plurality of pixels, and the pixels each include first and second light-receiving devices, first to fifth transistors, a capacitor, and a first wiring. One electrode of the first light-receiving device is electrically connected to the first wiring, and the other electrode is electrically connected to one of a source and a drain of the first transistor. One electrode of the second light-receiving device is electrically connected to the first wiring, and the other electrode is electrically connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor, one of a source and a drain of the third transistor, and a gate of the fourth transistor.

公开(公告)号：US20240188330A1

公开(公告)日：2024-06-06

申请号：US18517122

申请日：2023-11-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji KUSUNOKI ,  Hideaki SHISHIDO ,  Susumu KAWASHIMA ,  Motoharu SAITO ,  Tomoaki ATSUMI

IPC: H10K59/121 ,  G09G3/3233 ,  H10K59/124

CPC classification number: H10K59/1213 ,  G09G3/3233 ,  H10K59/124 ,  G09G2300/0465 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/08 ,  G09G2330/021

Abstract: A novel semiconductor device is provided. A gate of a second transistor is electrically connected to one of a source and a drain of a first transistor and one of a source and a drain of a third transistor. Aback gate of the second transistor is electrically connected to one of a source and a drain of a fourth transistor and one terminal of a first capacitor. One of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor, the other terminal of the first capacitor, and one terminal of a light-emitting element. A semiconductor layer in each of the first, third, and fourth transistors is partly in an opening formed in an insulating layer.

公开(公告)号：US20240185800A1

公开(公告)日：2024-06-06

申请号：US18576197

申请日：2022-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Susumu KAWASHIMA ,  Tomoaki ATSUMI

IPC: G09G3/3266 ,  G09G3/3225

CPC classification number: G09G3/3266 ,  G09G3/3225 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A semiconductor device capable of performing authentication in a short time and a driving method thereof are provided. A semiconductor device including a light-emitting apparatus and an imaging apparatus and a driving method thereof. The imaging apparatus includes pixels arranged in a matrix and a row driver including a shift register circuit. The driving method includes a first mode and a second mode. The first mode includes a step of detecting a position of a finger of a user. The second mode includes a step of reading out an image of a fingerprint of the user from pixels in the first row to a row of the position where the fingerprint of the user is detected in the first mode, row by row. The operation of the shift register circuit is stopped after the first mode and the second mode are completed.

公开(公告)号：US20240144879A1

公开(公告)日：2024-05-02

申请号：US18279110

申请日：2022-02-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Satoshi YOSHIMOTO ,  Susumu KAWASHIMA ,  Kazunori WATANABE ,  Tomoaki ATSUMI ,  Koji KUSUNOKI

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  H10K59/35

Abstract: Provided is a highly reliable semiconductor device. The present invention relates to a shift register circuit including a plurality of stages of sequential circuits. An output signal of a sequential circuit is input to a sequential circuit in the subsequent stage. Before a sequential circuit outputs a signal and after the sequential circuit outputs the signal, the potential of a gate of a transistor included in the sequential circuit is changed in accordance with a clock signal so as to avoid voltage stress application between the gate and a source of the transistor for a long time. The shift register circuit can be applied to a scan line driver circuit of a display apparatus, for example.

公开(公告)号：US20240049543A1

公开(公告)日：2024-02-08

申请号：US18266847

申请日：2021-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji KUSUNOKI ,  Kazunori WATANABE ,  Satoshi YOSHIMOTO ,  Tomoaki ATSUMI ,  Daisuke KUBOTA ,  Naoto KUSUMOTO

IPC: H10K59/131 ,  H10K59/80

CPC classification number: H10K59/1315 ,  H10K59/80522

Abstract: A high-resolution display device with reduced display unevenness is provided. In the display device, a plurality of pixels are included over a substrate; each of the plurality of pixels includes a transistor and a light-emitting element; the light-emitting element includes a first electrode, an EL layer over the first electrode, and a second electrode over the EL layer; the first electrode is electrically connected to the transistor; in the plurality of pixels, the first electrodes in adjacent pixels are separated by an insulating layer; the second electrode includes a conductive material having light-transmitting property with respect to visible light; the second electrode of each of the plurality of pixels is shared; and light is emitted from the second electrode side. A wiring is included; in a plane view with respect to the substrate, the wiring is placed in a region where the EL layer is not placed; and the second electrode is placed over and in contact with the wiring.

公开(公告)号：US20210287732A1

公开(公告)日：2021-09-16

申请号：US17337552

申请日：2021-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Shuhei MAEDA

IPC: G11C11/4094 ,  H01L27/108 ,  H01L29/786

Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.

公开(公告)号：US20210273110A1

公开(公告)日：2021-09-02

申请号：US17261665

申请日：2019-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L27/108

Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.