-
公开(公告)号：US20180181394A1
公开(公告)日：2018-06-28
申请号：US15387823
申请日：2016-12-22
申请人： Vinodh Gopal , James D. Guilford
发明人： Vinodh Gopal , James D. Guilford
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30109 , G06F9/30112 , G06F15/8007
摘要： Processor instructions for determining two minimum and two maximum values and associated apparatus and methods. The instructions include various 2MIN instructions for determining the two smallest values among three or four input values and 2MAX instructions for determining the two largest values among three or four input values. The 2MIN instructions employ two operands, with the first operand in some of the variations storing concatenated min1 and min2 values in a first register and a scr2 comparison value or two src2 concatenated src2 values in a second register. Comparators are used to implement hardware logic for determining whether the scr2 value(s) is/are less than each of min1 and min2. Based on the hardware logic, the smallest two values among min1, min2, and src2 (or both src2 values) are stored as concatenated values in the first register. The 2MAX instructions are implemented in a similar manner, except the comparisons are whether the scr2 value(s) is/are greater than each of max1 and max2 values. 128-bit 2MIN and 2MAX SIMD instructions are also provided for processing two 64-bit data-paths in parallel.
-
62.发明申请公开(公告)号：US20170177404A1
公开(公告)日：2017-06-22
申请号：US14975847
申请日：2015-12-20
CPC分类号： G06F9/466 , G06F9/5061 , G06F9/544 , G06F9/546 , G06F2209/509
摘要： Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.
-
公开(公告)号：US20170187388A1
公开(公告)日：2017-06-29
申请号：US14757854
申请日：2015-12-26
CPC分类号： H03M7/3082 , G06F9/3877 , G06F9/46 , H03M7/4037 , H03M7/6005 , H03M7/6011 , H03M7/6017 , H03M7/6052
摘要： Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.
-
64.发明申请METHOD AND APPARATUS TO PROCESS 4-OPERAND SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION 有权过程4操作的方法和装置SIMD INTEGER MULTIPLY-ACCUMULATE指令公开(公告)号：US20140082328A1
公开(公告)日：2014-03-20
申请号：US13617021
申请日：2012-09-14
CPC分类号： G06F9/3001 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/30145 , G06F9/3016 , G06F9/34 , G06F9/3887
摘要： According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
摘要翻译： 根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。 第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。 所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到 基于第四操作数的累计值。
-
公开(公告)号：US20160283504A1
公开(公告)日：2016-09-29
申请号：US14671605
申请日：2015-03-27
IPC分类号： G06F17/30
CPC分类号： G06F17/30153 , H03M7/3084 , H03M7/3088 , H03M7/4006
摘要： A processor includes a memory hierarchy, buffer, and a compression module. The compression module includes logic to evaluate a stream of data to be compressed according to a compression scheme, selectively modify a format of the compression scheme based upon a number of literals received, compress a sequence of the data to produce the output data sequence, and send the output data sequence to the memory hierarchy.
摘要翻译： 处理器包括存储器层级，缓冲器和压缩模块。 压缩模块包括根据压缩方案来评估要压缩的数据流的逻辑，基于所接收的文字数量选择性地修改压缩方案的格式，压缩数据序列以产生输出数据序列;以及 将输出数据序列发送到存储器层次结构。
-
66.发明授权Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction 有权处理4操作数SIMD整数乘法累加指令的方法和装置公开(公告)号：US09292297B2
公开(公告)日：2016-03-22
申请号：US13617021
申请日：2012-09-14
CPC分类号： G06F9/3001 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/30145 , G06F9/3016 , G06F9/34 , G06F9/3887
摘要： According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
摘要翻译： 根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。 第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。 所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到 基于第四操作数的累计值。
-
公开(公告)号：US07337275B2
公开(公告)日：2008-02-26
申请号：US10218682
申请日：2002-08-13
IPC分类号： G06F12/00
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901 , H04L49/9031
摘要： A method of managing a free list and ring data structure, which may be used to store journaling information, by storing and modifying information describing a structure of the free list or ring data structure in a cache memory that may also be used to store information describing a structure of a queue of buffers.
摘要翻译： 一种管理可用于存储日志信息的空闲列表和环形数据结构的方法，通过将描述自由列表或环形数据结构的结构的信息存储和修改，该缓存信息可以用于存储描述信息的信息 缓冲区队列的结构。
-
公开(公告)号：US07478374B2
公开(公告)日：2009-01-13
申请号：US10807218
申请日：2004-03-22
申请人： James D. Guilford
发明人： James D. Guilford
IPC分类号： G06F9/45
CPC分类号： G06F11/3624
摘要： An assembler, which can be provided as part of a debugger and/or development system, avoids register allocation errors, such as register bank conflicts and/or insufficient physical registers, automatically.
摘要翻译： 可以作为调试器和/或开发系统的一部分提供的汇编器自动避免寄存器分配错误，如寄存器组冲突和/或不足的物理寄存器。
-
69.发明授权公开(公告)号：US07020871B2
公开(公告)日：2006-03-28
申请号：US09747019
申请日：2000-12-21
申请人： Debra Bernstein , Serge Kornfeld , Desmond R. Johnson , Donald F. Hooper , James D. Guilford , Richard D. Muratori
发明人： Debra Bernstein , Serge Kornfeld , Desmond R. Johnson , Donald F. Hooper , James D. Guilford , Richard D. Muratori
IPC分类号： G06F9/44
CPC分类号： G06F11/362
摘要： A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.
摘要翻译： 调试在具有微引擎的多线程处理器中执行的代码的方法包括从连接到处理器的远程用户界面接收表示所选择的一个微引擎中的所选择的一个微指令的标识，所述远程用户界面暂停在所选择的微引擎中执行的线程中的程序执行， 在所选择的微引擎中的程序指令之后插入与从远程用户界面接收的程序指令相匹配的断点，恢复所选微引擎中的程序执行，执行断点程序，如果所选择的微引擎中的程序执行遇到断点并恢复程序执行 微型发动机。
-
公开(公告)号：US06684395B2
公开(公告)日：2004-01-27
申请号：US09753084
申请日：2000-12-28
IPC分类号： G06F944
CPC分类号： G06F9/44521
摘要： A method and mechanism for executing an application by a processor in a multi-processor configuration of processors, each having an associated instruction memory is presented. The application receives object code that includes an image for at least one other processor in the multi-processor configuration of processors. The application binds an import variable in the image to a parameter value and stores the image for the at least one other processor into the associated instruction memory.
摘要翻译： 提出了一种用于在处理器的多处理器配置中由处理器执行应用的方法和机制，每个处理器具有相关联的指令存储器。 该应用接收处理器的多处理器配置中的至少一个其他处理器的图像的目标代码。 应用程序将图像中的导入变量绑定到参数值，并将至少一个其他处理器的映像存储到相关联的指令存储器中。
-
-
-
-
-
-
-
-
-
搜索结果
74 条记录 (耗时 0.031 秒)
