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    INSTRUCTION SET FOR VARIABLE LENGTH INTEGER CODING
    2.
    发明申请
    INSTRUCTION SET FOR VARIABLE LENGTH INTEGER CODING 审中-公开

    公开(公告)号：US20180095760A1

    公开(公告)日：2018-04-05

    申请号：US15281380

    申请日：2016-09-30

    申请人： James D. Guilford ,  Vinodh Gopal

    发明人： James D. Guilford ,  Vinodh Gopal

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3016 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30192

    摘要： Instruction sets for variable length integer (varint) coding and associated methods and apparatus. The instructions sets include instructions for encoding and decoding varints, and may be included as a part of an instruction set architecture (ISA) for processors architectures such as x86 and Arm-based architectures, as well as other ISAs. In one aspect, the instructions include, a varint size encode instruction to encode a size of a varint, a varint encode instruction to encode a varint, a varint size decode instruction to decode a size of an encoded varint, and a varint decode instruction to decode an encoded varint. Varint encode size and encode instructions may be combined in a single instructions. Similarly, varint decode size and decode instructions may be combined in a single instruction. In one aspect, the instructions use a variable-length quantity (VLQ) encoding scheme under which varints are encoded into one or more VLQ octets.

    Digest generation
    4.
    发明授权
    Digest generation 有权
    消化一代

    公开(公告)号：US09292548B2

    公开(公告)日：2016-03-22

    申请号：US13995236

    申请日：2011-11-01

    申请人： Vinodh Gopal ,  James D. Guilford ,  Schuyler Eldridge ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Wajdi K. Feghali

    发明人： Vinodh Gopal ,  James D. Guilford ,  Schuyler Eldridge ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Wajdi K. Feghali

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30303 ,  G06F17/30306 ,  G06F17/3033

    摘要： In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.

    摘要翻译： 在一个实施例中，电路可以生成待组合的摘要以产生散列值。 摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。 电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。 所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。 在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

    Efficient multiplication, exponentiation and modular reduction implementations
    5.
    发明授权
    Efficient multiplication, exponentiation and modular reduction implementations 有权
    有效的乘法，乘法和模块化削减实现

    公开(公告)号：US09092645B2

    公开(公告)日：2015-07-28

    申请号：US13994782

    申请日：2011-12-05

    申请人： Erdinc Ozturk ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Deniz Karakoyunlu ,  Martin G. Dixon ,  Kahraman D. Akdemir

    发明人： Erdinc Ozturk ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Deniz Karakoyunlu ,  Martin G. Dixon ,  Kahraman D. Akdemir

    IPC分类号： H04L29/00 ,  G06F21/71 ,  H04L9/30

    CPC分类号： G06F21/71 ,  G06F7/723 ,  H04L9/3006 ,  H04L2209/12

    摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.

    摘要翻译： 在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是 指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

    EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS
    6.
    发明申请
    EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS 有权
    有效的实施，授权和模块化的减少实施

    公开(公告)号：US20150082047A1

    公开(公告)日：2015-03-19

    申请号：US13994782

    申请日：2011-12-05

    申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Deniz Karakoyunlu ,  Martin G. Dixon ,  Kahraman D. Akdemir

    发明人： Erdinc Ozturk ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Deniz Karakoyunlu ,  Martin G. Dixon ,  Kahraman D. Akdemir

    IPC分类号： G06F21/71 ,  H04L9/30

    CPC分类号： G06F21/71 ,  G06F7/723 ,  H04L9/3006 ,  H04L2209/12

    摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.

    摘要翻译： 在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是 指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

    SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION FOR MULTI-PRECISION ARITHMETIC
    7.
    发明申请
    SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION FOR MULTI-PRECISION ARITHMETIC 有权
    用于多精度算术的SIMD整数多项式累积指令

    公开(公告)号：US20140237218A1

    公开(公告)日：2014-08-21

    申请号：US13992728

    申请日：2011-12-19

    申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  James D. Guilford ,  Kirk S. Yap ,  Sean M. Gulley ,  wajdi K. Feghali ,  Martin G. Dixon

    发明人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  James D. Guilford ,  Kirk S. Yap ,  Sean M. Gulley ,  wajdi K. Feghali ,  Martin G. Dixon

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3001 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3893

    摘要： A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.

    摘要翻译： 乘法和累加（MAC）指令允许有效执行无符号整数乘法。 MAC指令表示作为第一操作数的第一向量寄存器，作为第二操作数的第二向量寄存器和作为目的地的第三向量寄存器。 第一向量寄存器存储第一因子，第二向量寄存器存储部分和。 执行MAC指令以将第一因子与隐式第二因子相乘以生成乘积，并将部分和添加到乘积以生成结果。 第一个因素，隐含的第二个因子和部分和具有相同的数据宽度，产品的数据宽度是两倍。 结果的最大一半存储在第三向量寄存器中，结果的最低有效半存储在第二向量寄存器中。

    METHODS, SYSTEMS AND APPARATUS TO REDUCE PROCESSOR DEMANDS DURING ENCRYPTION
    8.
    发明申请
    METHODS, SYSTEMS AND APPARATUS TO REDUCE PROCESSOR DEMANDS DURING ENCRYPTION 有权
    在加密过程中减少处理器数量的方法，系统和设备

    公开(公告)号：US20140177823A1

    公开(公告)日：2014-06-26

    申请号：US13727141

    申请日：2012-12-26

    申请人： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford

    发明人： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0637 ,  G06F9/00 ,  G06F9/30032 ,  G06F21/00 ,  H04L2209/12

    摘要： Methods and apparatus are disclosed to reduce processor demands during encryption. A disclosed example method includes detecting a request for the processor to execute an encryption cipher determining whether the encryption cipher is associated with a byte reflection operation, preventing the byte reflection operation when a buffer associated with the encryption cipher will not cause a carryover condition, and incrementing the buffer via a shift operation before executing the encryption cipher.

    摘要翻译： 公开了减少加密期间处理器需求的方法和装置。 所公开的示例方法包括：检测处理器执行确定加密密码是否与字节反射操作相关联的加密密码的请求，当与加密密码相关联的缓冲器不会导致携带条件时，防止字节反射操作;以及 在执行加密密码之前通过移位操作递增缓冲区。

    INSTRUCTION SET FOR MESSAGE SCHEDULING OF SHA256 ALGORITHM
    9.
    发明申请
    INSTRUCTION SET FOR MESSAGE SCHEDULING OF SHA256 ALGORITHM 有权
    SHA256算法的消息调度指令集

    公开(公告)号：US20140093069A1

    公开(公告)日：2014-04-03

    申请号：US13631165

    申请日：2012-09-28

    申请人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Vinodh Gopal ,  Sean M. Gulley

    发明人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Vinodh Gopal ,  Sean M. Gulley

    IPC分类号： H04L9/28

    CPC分类号： G09C1/00 ,  G06F9/30007 ,  H04L9/0643 ,  H04L2209/125

    摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.

    摘要翻译： 处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组 消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。 所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及 第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。