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    Systems and Methods for Enhanced Media Defect Detection
    61.
    发明申请
    Systems and Methods for Enhanced Media Defect Detection 有权
    增强介质缺陷检测的系统和方法

    公开(公告)号：US20100226033A1

    公开(公告)日：2010-09-09

    申请号：US12399713

    申请日：2009-03-06

    申请人： Weijun Tan ,  Hongwei Song ,  Shaohua Yang

    发明人： Weijun Tan ,  Hongwei Song ,  Shaohua Yang

    IPC分类号： G11B5/09

    CPC分类号： G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  H03M13/3905

    摘要： Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.

    摘要翻译： 本发明的各种实施例提供了用于检测存储介质缺陷的系统和方法。 作为一个示例，公开了一种媒体缺陷检测系统，其包括将检测算法应用于数据输入并提供硬输出和软输出的数据检测器电路。 第一电路将硬输出的一阶导数与数据输入的导数组合以产生第一组合信号。 第二电路将硬输出的二阶导数与第一组合信号的导数组合以产生第二组合信号。 第三电路将软输出的导数与第二组合信号和阈值组合以产生缺陷信号。

    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
    62.
    发明申请
    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
    用于读通道的可编程准循环低密度奇偶校验（QC LDPC）编码器

    公开(公告)号：US20100100788A1

    公开(公告)日：2010-04-22

    申请号：US12288221

    申请日：2008-10-17

    申请人： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    发明人： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    IPC分类号： H03M13/27 ,  G06F11/10

    CPC分类号： H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

    摘要： The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    摘要翻译： 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

    Method for detecting short burst errors in LDPC system
    63.
    发明申请
    Method for detecting short burst errors in LDPC system 有权
    用于检测LDPC系统中短脉冲串错误的方法

    公开(公告)号：US20100091629A1

    公开(公告)日：2010-04-15

    申请号：US12287959

    申请日：2008-10-15

    申请人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

    发明人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

    IPC分类号： G11B27/36

    CPC分类号： H03M13/1128 ,  H03M13/17

    摘要： The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

    摘要翻译： 本发明是用于检测短脉冲串错误的装置。 该设备包括第一信号输入，其中第一信号输入被配置为接收第一信号。 该设备包括第二信号输入，其中第二信号输入被配置为接收第二信号。 该装置包括逻辑门，其中逻辑门可操作用于接收第一信号输入端，第一信号输入端，经由第二信号输入端接收第二信号，并根据接收到的第一信号和第二信号产生逻辑输出门信号 信号。 此外，该器件包括滤波器，其中滤波器被配置为从逻辑门接收逻辑输出门信号，并且基于接收的逻辑输出门信号产生滤波器输出信号，其中滤波器输出信号可用于标记误差。

    Systems and methods for data detection including dynamic scaling
    66.
    发明授权
    Systems and methods for data detection including dynamic scaling 有权
    用于数据检测的系统和方法，包括动态缩放

    公开(公告)号：US08683306B2

    公开(公告)日：2014-03-25

    申请号：US12651547

    申请日：2010-01-04

    申请人： Shaohua Yang ,  Weijun Tan ,  Zongwang Li ,  Kiran Gunnam

    发明人： Shaohua Yang ,  Weijun Tan ,  Zongwang Li ,  Kiran Gunnam

    IPC分类号： H03M13/03

    CPC分类号： H03M13/1105 ,  H03M13/2957 ,  H03M13/3961 ,  H03M13/6325 ,  H03M13/658 ,  H04L1/005 ,  H04L1/0057

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，公开了一种包括信道检测器电路的数据处理系统。 信道检测器电路包括分支度量计算器电路，其可操作以从前一级接收多个违反的检查，并且使用至少部分地基于违反检查的数量选择的标量来缩放固有分支度量，以产生 缩放的内在分支度量。

    Systems and methods for hard decision assisted decoding
    69.
    发明授权
    Systems and methods for hard decision assisted decoding 有权
    硬判决辅助解码的系统和方法

    公开(公告)号：US08443267B2

    公开(公告)日：2013-05-14

    申请号：US12430927

    申请日：2009-04-28

    申请人： Hao Zhong ,  Shaohua Yang ,  Weijun Tan ,  Changyou Xu ,  Yuan Xing Lee

    发明人： Hao Zhong ,  Shaohua Yang ,  Weijun Tan ,  Changyou Xu ,  Yuan Xing Lee

    IPC分类号： G06F11/00

    CPC分类号： H03M13/1111 ,  H03M13/1108 ,  H03M13/1128 ,  H03M13/3715 ,  H03M13/6331

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，公开了一种包括具有数据检测器和软判决解码器的处理环路电路的数据处理系统。 数据检测器提供检测输出，软判决解码器将软解码算法应用于检测输出的导数，以产生软决策输出和第一硬决策输出。 该系统还包括排队缓冲器和硬判决解码器。 排队缓冲器可操作以存储软判决输出，并且硬判决解码器访问软决策输出并应用硬解码算法以产生第二硬决策输出。 如果软判决解码器和硬判决解码器不能收敛，则数据检测器可操作以对软决策输出的导数执行数据检测。