公开(公告)号：US5835488A

公开(公告)日：1998-11-10

申请号：US645584

申请日：1996-05-14

申请人： Takehiro Sugita

发明人： Takehiro Sugita

IPC分类号： H03K3/84 ,  G06F7/58 ,  H04B1/707 ,  H04B7/26 ,  H04J13/10 ,  H04B7/216 ,  H04B1/69 ,  H04J13/02 ,  H04J13/04

CPC分类号： H04J13/10 ,  G06F7/584 ,  H04B1/707 ,  H04J13/0022

摘要： A pseudo random noise sequence code generating circuit has a sequence generator (11) for sequentially generating a maximum length linear code sequence at an N-chip cycle and a first to (N-1)th vector multiplier (12 to 14) for obtaining values of skipped portions in the sequence generator by vector multiplication. It does so on the basis of the state value (S1) of a register forming the sequence generator, and generates a successive pseudo random noise sequence code based on an output of the sequence generator (PN1) and outputs of the first to the (N-1)th vector multiplier (PN2 to PN4). Thereby, the operating rate can be reduced to 1/N as compound to the prior art, and the operating voltage and electric power consumption can be reduced.

摘要翻译： 伪随机噪声序列码产生电路具有顺序生成器（11），用于顺序生成N码片周期的最大长度线性码序列，以及用于获得值的第一至第（N-1）个矢量乘法器（12至14） 通过矢量乘法在序列发生器中跳过的部分。 它基于形成序列发生器的寄存器的状态值（S1），并且基于序列发生器（PN1）的输出产生连续的伪随机噪声序列码，并且将第一到第（N -1）向量乘法器（PN2至PN4）。 由此，作为现有技术的化合物，工作速度可以降低到1 / N，并且可以降低工作电压和电力消耗。

公开(公告)号：US5757766A

公开(公告)日：1998-05-26

申请号：US650266

申请日：1996-05-22

申请人： Takehiro Sugita

发明人： Takehiro Sugita

IPC分类号： H04J11/00 ,  H04L5/02 ,  H04L27/26 ,  H04K1/10

CPC分类号： H04L27/2647 ,  H04B1/707 ,  H04L27/2626 ,  H04L5/026

摘要： In a communication system, the energy of each bit of the inputted information bit string is diffused over the whole frequency band of the orthogonal carriers, and the energy of the plural bits is multiplexed onto each orthogonal carrier, As a result, even though frequency selective fading has occurred attenuation value of the energy of each bit is some remarkable degrading of the error rate can be alleviated, and changing of the data rate can be easily accommodated by modifying the number of the code multiplexing. In this way, a communication system can be realized which is able to alleviate the performance deterioration due to frequency selective fading, and to easily cope with a modification of the data rate.

摘要翻译： 在通信系统中，输入的信息比特串的每个比特的能量在正交载波的整个频带上扩散，并且多个比特的能量被复用到每个正交载波上。结果是，即使频率选择 衰落已经发生衰减值每个位的能量有一些显着的降级，可以减轻错误率，并且可以通过修改代码复用的数量来容易地改变数据速率。 以这种方式，可以实现能够减轻由于频率选择性衰落引起的性能劣化的通信系统，并且容易地应对数据速率的修改。

公开(公告)号：US5745521A

公开(公告)日：1998-04-28

申请号：US824349

申请日：1997-03-26

申请人： Takehiro Sugita

发明人： Takehiro Sugita

IPC分类号： H04W24/00 ,  H03G3/30 ,  H04B1/707 ,  H04B7/005 ,  H04B7/26 ,  H04J13/00 ,  H04W52/52 ,  H04W72/08 ,  H04W76/02

CPC分类号： H04W52/52 ,  H03G3/3052 ,  H04B1/707 ,  H04B7/2628

摘要： A spread spectrum communication apparatus for communication with a plurality of communication units includes a reception circuit, an automatic gain control circuit, a spread spectrum code detection circuit, and a synthesis circuit. The reception circuit receives signals of a frequency channel inclusive of a target communication unit. The automatic gain control circuit controls the signal intensity of the frequency channel received by the reception circuit to a constant level. The spread spectrum code detection circuit detects the signal intensity of the spread spectrum code of the target communication unit from an output signal of the automatic gain control circuit. The synthesis circuit combines the signal intensity which is based on a gain control signal of the automatic gain control means with a signal intensity as detected by the spread spectrum code detection circuit to find a reception intensity.

摘要翻译： 用于与多个通信单元通信的扩频通信装置包括接收电路，自动增益控制电路，扩频码检测电路和合成电路。 接收电路接收包括目标通信单元的频率信道的信号。 自动增益控制电路将由接收电路接收的频道的信号强度控制在一定水平。 扩频码检测电路根据自动增益控制电路的输出信号检测目标通信单元的扩频码的信号强度。 合成电路将基于自动增益控制装置的增益控制信号的信号强度与由扩频码检测电路检测的信号强度相结合，以找到接收强度。

公开(公告)号：US5699380A

公开(公告)日：1997-12-16

申请号：US533761

申请日：1995-09-26

申请人： Takehiro Sugita

发明人： Takehiro Sugita

IPC分类号： H04B1/707 ,  H04B1/7117 ,  H04B7/26 ,  H04W88/02 ,  H04K1/00 ,  H04L1/02

CPC分类号： H04B1/70752 ,  H04B1/7117 ,  H04J13/0003

摘要： A number of demodulators receive a signal transmitted from a certain base station and propagated via different respective propagation paths. Each demodulator generates a demodulated signal by examining the correlation between the received signal and a pseudo-noise (PN) spread code. A system time managing counter has a count value that is initialized at the timing of the forefront of the spread code in the modulator when at least one of the demodulators starts the demodulating process after power-on or after a reset operation. A signal combiner combines the demodulated signals that are adjusted to coincide in timing with each other from the demodulators at a timing determined by a system time managing counter after initialization and provides a combined demodulated signal. A control circuit reads the information of the time offset of the PN code to the system time from the sync channel message on a sync channel in the synthetic demodulated signal, so that the system time of the base station is set to the system time managing counter.

摘要翻译： 多个解调器接收从某个基站发送的信号并通过不同的相应传播路径进行传播。 每个解调器通过检查接收信号和伪噪声（PN）扩展码之间的相关性来产生解调信号。 当至少一个解调器在上电或复位操作之后开始解调处理时，系统时间管理计数器具有在调制器中的扩展码的最前面的定时被初始化的计数值。 信号组合器将在经过初始化之后由系统时间管理计数器确定的定时从调制器中将被调整为调整的解调信号相互重合，并提供组合的解调信号。 控制电路从合成解调信号的同步信道上的同步信道消息中读取PN码的时间偏移信息到系统时间，从而将基站的系统时间设置为系统时间管理计数器 。

公开(公告)号：US4612627A

公开(公告)日：1986-09-16

申请号：US560956

申请日：1983-12-13

申请人： Takehiro Sugita ,  Akira Sakamoto ,  Takeshi Fukami ,  Michimasa Komatsubara ,  Akira Shimizu

发明人： Takehiro Sugita ,  Akira Sakamoto ,  Takeshi Fukami ,  Michimasa Komatsubara ,  Akira Shimizu

IPC分类号： H04K1/00 ,  G06F17/17 ,  G11B20/10 ,  G11B27/038 ,  H04K1/06 ,  H04L9/34 ,  G06F7/52

CPC分类号： G11B20/10527 ,  G11B27/038 ,  H04K1/06

摘要： A digital signal composing circuit includes a first selector for selecting a plurality of digital data, a second selector for selecting one of the digital data and a feedback signal, a control circuit for controlling the switching of the first and second selectors and an adding circuit for adding outputs of the first and second selectors and supplying the added output to the second selector as the feedback signal wherein the final output is derived from the adding circuit. Thus, without using any multiplier, the signal processing can be widely used in the digital signal processing such as digital volume, cross-fade, fade-in/-out, mixing, linear interpolation and the like.

摘要翻译： 数字信号组合电路包括：用于选择多个数字数据的第一选择器，用于选择数字数据和反馈信号之一的第二选择器，用于控制第一和第二选择器的切换的控制电路和用于 添加第一选择器和第二选择器的输出，并将添加的输出提供给第二选择器作为反馈信号，其中最终输出从加法电路导出。 因此，在不使用任何乘法器的情况下，信号处理可广泛用于诸如数字音量，交叉淡入淡出，淡入/淡出，混合，线性插值等数字信号处理。

公开(公告)号：US08625706B2

公开(公告)日：2014-01-07

申请号：US12784026

申请日：2010-05-20

申请人： Tatsuo Shimizu ,  Takehiro Sugita

发明人： Tatsuo Shimizu ,  Takehiro Sugita

IPC分类号： H04L25/49

CPC分类号： H04L7/0008 ,  H04L7/06

摘要： Provided is a signal processing apparatus including an encoder for encoding, according to respective specific coding schemes, a first bit string formed from bit values at odd-numbered positions and a second bit string formed from bit values at even-numbered positions that are obtained by alternately extracting bit values from a bit string that is expressed by mutually different first and second bit values, and generating first and second encoded signals that do not include a DC component, and a signal generation unit for generating a multilevel signal by respectively adding, to a clock signal having larger amplitude than the first and second encoded signals that are generated by the encoder, the first encoded signal in synchronization with a timing of the clock signal being at a positive amplitude value and the second encoded signal in synchronization with a timing of the clock signal being at a negative amplitude value.

摘要翻译： 提供了一种信号处理装置，包括编码器，根据各自的特定编码方案，编码由奇数位置的比特值形成的第一比特串，以及由偶数位置的比特值形成的第二比特串， 交替地从由相互不同的第一和第二比特值表示的比特串中提取比特值，以及生成不包括DC分量的第一和第二编码信号;以及信号生成单元，用于通过分别将 具有比由编码器产生的第一和第二编码信号大的振幅的时钟信号，与时钟信号的定时同步的第一编码信号处于正振幅值，并且第二编码信号与 时钟信号处于负振幅值。

公开(公告)号：US08619899B2

公开(公告)日：2013-12-31

申请号：US12550441

申请日：2009-08-31

申请人： Takehiro Sugita ,  Kunio Fukuda

发明人： Takehiro Sugita ,  Kunio Fukuda

IPC分类号： H04L25/34

CPC分类号： H04L25/0272 ,  H04B3/44 ,  H04L25/4904 ,  H04L25/4917

摘要： There is provided an information processing apparatus, including a signal receiver that receives a signal encoded in such a way that a signal containing a first bit value and a second bit value, wherein the first bit value is represented by first amplitude values, the second value is represented by a second amplitude value, and polarity of the encoded signal amplitude value is reversed in each period, a conversion processor performs conversion to add a delayed signal that is delayed by delaying a signal received by the signal receiver by one period of the received signal, an inversion processor that performs inverse processing of the conversion on the signal output from the conversion processor, and an input data decoder that decodes an input data by determining the first and second values based on the amplitude value of the signal output from the inversion processor.

摘要翻译： 提供了一种信息处理装置，包括信号接收器，该信号接收器接收以包含第一位值和第二位值的信号编码的信号，其中第一位值由第一幅度值表示，第二值 由第二振幅值表示，并且编码信号振幅值的极性在每个周期中反转，转换处理器执行转换，以将通过将由信号接收器接收的信号延迟一段时间来延迟的延迟信号 信号，对从转换处理器输出的信号执行转换的逆处理的反转处理器，以及基于从反演输出的信号的振幅值确定第一和第二值来对输入数据进行解码的输入数据解码器 处理器。

公开(公告)号：US08089176B2

公开(公告)日：2012-01-03

申请号：US12333068

申请日：2008-12-11

申请人： Kazuji Sasaki ,  Takehiro Sugita ,  Kunio Fukuda

发明人： Kazuji Sasaki ,  Takehiro Sugita ,  Kunio Fukuda

IPC分类号： H02J1/00 ,  H02J3/00 ,  H04B3/54

CPC分类号： H04B3/56 ,  H04B3/54 ,  H04B2203/5441 ,  H04B2203/5491 ,  Y10S307/01

摘要： Disclosed herein is a communication system including: at least one power line communication apparatus connected via a general power line for supplying a commercial alternate current power; a communication terminal having a modem for power line communication, and a plurality of first coils having different directivities; and a coupling apparatus, connected to a power line, having a filter for attenuating an alternate current component of the power line, and a second coil arranged after the filter; wherein the communication terminal executes mutual communication with any of the power line communication apparatus connected via the general power line through proximity communication based on an electromagnetic coupling action that is generated between the plurality of first coils and the second coil when the communication terminal is brought to the proximity of a coupling surface of the coupling apparatus.

摘要翻译： 本文公开了一种通信系统，包括：至少一个电力线通信装置，其经由用于提供商用交流电源的一般电力线连接; 具有用于电力线通信的调制解调器的通信终端和具有不同方向性的多个第一线圈; 以及连接到电力线的耦合装置，具有用于衰减电力线的交流分量的滤波器和布置在滤波器之后的第二线圈; 其中，所述通信终端通过基于在所述通信终端到达所述多个第一线圈与所述第二线圈之间产生的电磁耦合动作时，经由所述一般电力线路连接的所述电力线通信装置中的任一个进行相互通信 联接装置的联接表面的接近。

公开(公告)号：US20110222555A1

公开(公告)日：2011-09-15

申请号：US13108570

申请日：2011-05-16

申请人： Takehiro Sugita

发明人： Takehiro Sugita

IPC分类号： H04L12/43

CPC分类号： H04B3/542 ,  H04J3/1682

摘要： A communication apparatus is provided. The communication apparatus includes a first unit for performing data communication using a bandwidth reservation type transmission area constituted by a plurality of time-divided time slots via a power line to which an alternating-current voltage is supplied. A second unit is connected to the first unit, for securing a vacant time slot out of the plurality of time-divided time slots. A third unit is connected to the first unit, for securing a time slot out of the plurality of time-divided time slots when incapable of securing the vacant time slot, the secured time slot being used in common by a first communication system used by the communication apparatus and a second communication system different from the first communication system, the second communication system using the same communication procedure as the first communication system.

摘要翻译： 提供一种通信装置。 该通信装置包括：第一单元，用于经由经由提供交流电压的电力线由多个分时时隙构成的带宽预留型传输区域进行数据通信。 第二单元连接到第一单元，用于固定多个分时时隙中的空闲时隙。 第三单元连接到第一单元，用于在不能确保空闲时隙的情况下将多个时分时隙中的时隙固定，所述安全时隙由第一通信系统使用的第一通信系统共同使用 通信装置和与第一通信系统不同的第二通信系统，第二通信系统使用与第一通信系统相同的通信过程。

公开(公告)号：US20100329381A1

公开(公告)日：2010-12-30

申请号：US12784026

申请日：2010-05-20

申请人： Tatsuo Shimizu ,  Takehiro Sugita

发明人： Tatsuo Shimizu ,  Takehiro Sugita

IPC分类号： H04L25/49

CPC分类号： H04L7/0008 ,  H04L7/06

摘要： Provided is a signal processing apparatus including an encoder for encoding, according to respective specific coding schemes, a first bit string formed from bit values at odd-numbered positions and a second bit string formed from bit values at even-numbered positions that are obtained by alternately extracting bit values from a bit string that is expressed by mutually different first and second bit values, and generating first and second encoded signals that do not include a DC component, and a signal generation unit for generating a multilevel signal by respectively adding, to a clock signal having larger amplitude than the first and second encoded signals that are generated by the encoder, the first encoded signal in synchronization with a timing of the clock signal being at a positive amplitude value and the second encoded signal in synchronization with a timing of the clock signal being at a negative amplitude value.

摘要翻译： 提供了一种信号处理装置，包括编码器，根据各自的特定编码方案，编码由奇数位置的比特值形成的第一比特串，以及由偶数位置的比特值形成的第二比特串， 交替地从由相互不同的第一和第二比特值表示的比特串中提取比特值，以及生成不包括DC分量的第一和第二编码信号;以及信号生成单元，用于通过分别将 具有比由编码器产生的第一和第二编码信号大的振幅的时钟信号，与时钟信号的定时同步的第一编码信号处于正振幅值，并且第二编码信号与 时钟信号处于负振幅值。